Interconnect retimer enhancements

Patent metadata

Field	Value
Publication number	US-2016377679-A1
Application number	US-201315039515-A
Country	US
Kind code	A1
Filing date	Dec 26, 2013
Priority date	Dec 26, 2013
Publication date	Dec 29, 2016
Grant date	—

Abstract

A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

First claim

1 .- 33 . (canceled)

34 . An apparatus comprising:
control logic to:
generate a test mode signal to include a test pattern and an error reporting sequence; and
transmitter logic to:
send the test mode signal on a link to comprise one or more extension devices and two or more sublinks, wherein the test mode signal is to be sent on a particular one of the sublinks, the test pattern is to be used by a receiving device to identify errors on the particular sublink, and the error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

35 . The apparatus of claim 34 , wherein the test mode signal is sent within a loopback test mode and instances of the test mode signal are to be sent from a first device on the link over the one or more extension devices to a second device and further sent from the second device over the one or more extension devices back to the first device.

36 . The apparatus of claim 35 , further comprising receiver logic to receive at least one of the instances of the test mode signal from another device on another one of the sublinks of the link, wherein each instance of the test mode signal includes an instance of the test pattern and an instance of the error reporting sequence.

37 . The apparatus of claim 36 , further comprising error detection logic to determine one or more errors on the other sublink based on the instance of the test pattern.

38 . The apparatus of claim 37 , wherein errors are determined for a sublink based on an identification that an instance of the test pattern as included in a test mode signal received over the sublink deviates from an expected value for the test pattern.

39 . The apparatus of claim 34 , wherein the extension device comprises a retimer.

40 . The apparatus of claim 39 , wherein the apparatus comprises the retimer.

41 . The apparatus of claim 34 , wherein the error reporting sequence comprises a plurality of segments and each segment describes error status of a respective one of the sublinks.

42 . The apparatus of claim 41 , wherein each segment describes one of a downstream channel and an upstream channel of a respective sublink.

43 . The apparatus of claim 41 , wherein each segment comprises one or more ordered sets and at least a portion of each of the ordered sets is provided to be encoded to identify error status of at least one of the sublinks.

44 . The apparatus of claim 43 , wherein each ordered set comprises a respective skip (SKP) ordered set.

45 . The apparatus of claim 41 , wherein the one or more extension devices comprise at least two extension devices, the two or more sublinks comprise three sublinks, and the plurality of segments comprise at least five segments.

46 . The apparatus of claim 34 , wherein the control logic is to encode error information detected for a preceding sublink in the error reporting sequence and maintain error information in the error reporting sequence for previously detected error status of other sublinks in the two or more sublinks.

47 . The apparatus of claim 46 , wherein the error information includes one or more of: a number of errors detected for a sublink, a lane of the link on which an appeared, and a location of errors detected in a received test pattern.

48 . The apparatus of claim 34 , wherein the test pattern comprises a predefined pattern to be regenerated at each sublink during a test.

49 . The apparatus of claim 48 , wherein the test pattern includes one or more ordered sets.

50 . The apparatus of claim 49 , wherein the one or more ordered sets electrical idle exit sequence ordered set (EIEOS).

51 . The apparatus of claim 34 , wherein the control logic is to identify that the link is in a test mode, and the test mode signal is sent in accordance with the test mode.

52 . A method comprising:
identifying that a link is to enter a test mode, wherein the link comprises one or more extension devices and two or more sublinks; generating a test mode signal, wherein the test mode signal includes a test pattern and an error reporting sequence and the error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks; and sending the test mode signal within the test mode on a particular one of the sublinks.

53 . A system comprising:
a first device; a second device communicatively coupled to the first device using a link; one or more extension devices included on the link, wherein data is sent between the first and second devices over the extension devices; and test mode logic to:
send test mode signals within a test mode of the link, wherein the link comprises a plurality of sublinks, each instance of the test mode signal corresponds to a test of a respective one of the sublinks and includes a test pattern and an error reporting sequence, the test pattern is to be used by a device receiving the test mode signal to identify errors on the corresponding sublink, and the error reporting sequence is to be encoded with error information to describe error status determined for the sublinks.

54 . The system of claim 53 , wherein the test mode logic is further to:
receive test mode signals and assess the test pattern in the test mode signal to identify an error status of the sublink corresponding to the test mode signal.

55 . The system of claim 54 , wherein each of the extension devices and the first device include a respective instance of the test mode logic.

56 . The system of claim 55 , wherein the second device also includes an instance of the test mode logic.

57 . The system of claim 53 , further comprising reporting logic to record error status information for the plurality of sublinks determined from the test mode signals and included in the error reporting sequences in one or more registers corresponding to the link.

58 . The system of claim 53 , wherein the extension device comprises at least two retimers.

Assignees

• Intel Corp

Inventors

• Froelich Daniel S
• Das Sharma Debendra

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/2205

  using arrangements specific to the hardware being tested · CPC title

• G06F11/3688

  for test execution, e.g. scheduling of test suites · CPC title