Electronic devices having bilayer capping layers and/or barrier layers

Patent metadata

Field	Value
Publication number	US-11599210-B2
Application number	US-202217671768-A
Country	US
Kind code	B2
Filing date	Feb 15, 2022
Priority date	Jan 19, 2017
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

In various embodiments, electronic devices such as thin-film transistors and/or touch-panel displays incorporate bilayer capping layers and/or barrier layers.

First claim

What is claimed is:

1. An electronic device comprising:
a substrate; and
a conductive feature disposed over the substrate, the conductive feature comprising:
(a) disposed over the substrate, a conductor layer comprising at least one of Cu, Ag, Al, or Au, and
(b) disposed over the conductor layer, a bilayer capping layer comprising a base layer and a dielectric layer disposed thereover, wherein (i) the base layer comprises an alloy of Cu and/or Mo with 0.5 weight %-50 weight % of one or more anodizable alloying elements selected from the list consisting of Ta, Nb, Al, Hf, Zr, Ti, and Mg, and (ii) the dielectric layer comprises an oxide, nitride, or oxynitride of the one or more anodizable alloying elements.

2. The electronic device of claim 1 , wherein the substrate comprises glass.

3. The electronic device of claim 1 , wherein the substrate comprises silicon.

4. The electronic device of claim 3 , wherein the substrate comprises amorphous silicon.

5. The electronic device of claim 1 , wherein the base layer comprises an alloy of (i) Mo and Nb, (ii) Mo, Ta, and Nb, (iii) Mo, Nb, and Ti, (iv) Mo and Ti, or (v) Mo, Nb, and Zr.

6. The electronic device of claim 1 , wherein tithe base layer comprises an alloy of Cu, Ta, and Zr, and (ii) the base layer is substantially free of Mo.

7. The electronic device of claim 1 , wherein the dielectric layer is substantially free of Cu and/or Mo.

8. The electronic device of claim 1 , wherein the base layer comprises:
an interfacial portion disposed beneath and in contact with the dielectric layer; and
a bottom portion disposed beneath the interfacial portion.

9. The electronic device of claim 8 , wherein a concentration of at least one of the one or more anodizable alloying elements within the interfacial portion is less than a concentration of at least one of the one or more anodizable alloying elements within the bottom portion.

10. The electronic device of claim 8 , wherein the interfacial portion is substantially free of at least one of the one or more anodizable alloying elements.

11. The electronic device of claim 8 , wherein the interfacial portion is substantially free of all of said one or more anodizable alloying elements.

12. The electronic device of claim 1 , wherein the conductive feature comprises an electrode.

13. The electronic device of claim 1 , wherein the conductive feature comprises an interconnect.

14. The electronic device of claim 13 , wherein the conductive feature is electrically coupled to a conductive sensor.

15. The electronic device of claim 14 , wherein the conductive sensor comprises a substantially transparent conductive material.

16. The electronic device of claim 14 , wherein the conductive sensor comprises indium tin oxide.

17. The electronic device of claim 1 , wherein tithe base layer comprises an alloy of Mo with 0.5 weight %-50 weight % of one or more anodizable alloying elements selected from the list consisting of Ta, Nb, Al, Hf, Zr, Ti, and Mg, and (ii) the base layer is substantially free of Cu.

18. The electronic device of claim 1 , wherein tithe base layer comprises an alloy of Cu with 0.5 weight %-50 weight % of one or more anodizable alloying elements selected from the list consisting of Ta, Nb, Al, Hf, Zr, Ti, and Mg, and (ii) the base layer is substantially free of Cu.

19. The electronic device of claim 1 , wherein (i) the base layer comprises an alloy of Mo and Nb, and (ii) the base layer is substantially free of Cu.

20. The electronic device of claim 1 , wherein (i) the base layer comprises an alloy of Mo, Ta, and Nb, and (ii) the base layer is substantially free of Cu.

21. The electronic device of claim 1 , wherein (i) the base layer comprises an alloy of Mo, Nb, and Ti, and (ii) the base layer is substantially free of Cu.

22. The electronic device of claim 1 , wherein (i) the base layer comprises an alloy of Mo and Ti, and (ii) the base layer is substantially free of Cu.

23. The electronic device of claim 1 , wherein (i) the base layer comprises an alloy of Mo, Nb, and Zr, and (ii) the base layer is substantially free of Cu.

Assignees

• Starck H C Inc
• Materion Newton Inc

Inventors

• Jalili Helia
• Dary Francois
• Cox Barbara

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/032

  of conductive barrier, adhesion or liner layers · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10D86/40 Primary

  characterised by multiple TFTs · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title