Electronic devices having bilayer capping layers and/or barrier layers

Patent metadata

Field	Value
Publication number	US-10877582-B2
Application number	US-202016733412-A
Country	US
Kind code	B2
Filing date	Jan 3, 2020
Priority date	Jan 19, 2017
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

In various embodiments, electronic devices such as thin-film transistors and/or touch-panel displays incorporate bilayer capping layers and/or barrier layers.

First claim

What is claimed is:

1. A thin-film transistor comprising:
a substrate; and
an electrode comprising:
(a) disposed over the substrate, a conductor layer comprising at least one of Cu, Ag, Al, or Au, and
(b) disposed over the conductor layer, a bilayer capping layer comprising a base layer and a dielectric layer disposed thereover, wherein (i) the base layer comprises an alloy of Cu and/or Mo with 0.5 weight %-50 weight % of one or more anodizable alloying elements selected from the list consisting of Ta, Nb, Al, Hf, Zr, Ti, and Mg, and (ii) the dielectric layer comprises an oxide, nitride, or oxynitride of the one or more anodizable alloying elements.

2. The thin-film transistor of claim 1 , wherein the substrate comprises glass or silicon.

3. The thin-film transistor of claim 2 , wherein the substrate comprises amorphous silicon.

4. The thin-film transistor of claim 1 , wherein the base layer comprises an alloy of (i) Mo and Nb, (ii) Mo, Ta, and Nb, (iii) Mo, Nb, and Ti, (iv) Mo and Ti, or (v) Mo, Nb, and Zr.

5. The thin-film transistor of claim 1 , wherein the base layer comprises an alloy of Cu, Ta, and Zr.

6. The thin-film transistor of claim 1 , wherein the dielectric layer is substantially free of Cu and/or Mo.

7. The thin-film transistor of claim 1 , wherein the base layer comprises:
an interfacial portion disposed beneath and in contact with the dielectric layer; and
a bottom portion disposed beneath the interfacial portion.

8. The thin-film transistor of claim 7 , wherein a concentration of at least one of the one or more anodizable alloying elements within the interfacial portion is less than a concentration of at least one of the one or more anodizable alloying elements within the bottom portion.

9. The thin-film transistor of claim 7 , wherein the interfacial portion is substantially free of at least one of the one or more anodizable alloying elements.

10. The thin-film transistor of claim 7 , wherein the interfacial portion is substantially free of all of said one or more anodizable alloying elements.

11. A thin-film transistor comprising:
a substrate; and
an electrode comprising:
(a) disposed over the substrate, a bilayer barrier layer comprising a base layer and a dielectric layer disposed thereover, wherein (i) the base layer comprises an alloy of Cu and/or Mo with 0.5 weight %-50 weight % of one or more anodizable alloying elements selected from the list consisting of Ta, Nb, Al, Hf, Zr, Ti, and Mg, and (ii) the dielectric layer comprises an oxide, nitride, or oxynitride of the one or more anodizable alloying elements, and
(b) disposed over the barrier layer, a conductor layer comprising at least one of Cu, Ag, Al, or Au.

12. The thin-film transistor of claim 11 , wherein the substrate comprises glass or silicon.

13. The thin-film transistor of claim 12 , wherein the substrate comprises amorphous silicon.

14. The thin-film transistor of claim 11 , wherein the base layer comprises an alloy of (i) Mo and Nb, (ii) Mo, Ta, and Nb, (iii) Mo, Nb, and Ti, (iv) Mo and Ti, or (v) Mo, Nb, and Zr.

15. The thin-film transistor of claim 11 , wherein the base layer comprises an alloy of Cu, Ta, and Zr.

16. The thin-film transistor of claim 11 , wherein the dielectric layer is substantially free of Cu and/or Mo.

17. The thin-film transistor of claim 11 , wherein the base layer comprises:
an interfacial portion disposed beneath and in contact with the dielectric layer; and
a bottom portion disposed beneath the interfacial portion.

18. The thin-film transistor of claim 17 , wherein a concentration of at least one of the one or more anodizable alloying elements within the interfacial portion is less than a concentration of at least one of the one or more anodizable alloying elements within the bottom portion.

19. The thin-film transistor of claim 17 , wherein the interfacial portion is substantially free of at least one of the one or more anodizable alloying elements.

20. The thin-film transistor of claim 17 , wherein the interfacial portion is substantially free of all of said one or more anodizable alloying elements.

21. The thin-film transistor of claim 11 , wherein the electrode comprises, disposed over the conductor layer, a bilayer capping layer comprising a second base layer and a second dielectric layer disposed thereover, wherein (i) the second base layer comprises an alloy of Cu and/or Mo with 0.5 weight %-50 weight % of one or more second anodizable alloying elements selected from the list consisting of Ta, Nb, Al, Hf, Zr, Ti, and Mg, and (ii) the second dielectric layer comprises an oxide, nitride, or oxynitride of the one or more second anodizable alloying elements.

22. The thin-film transistor of claim 21 , wherein the base layer comprises an alloy the same as that of the second base layer.

23. The thin-film transistor of claim 21 , wherein the base layer comprises an alloy different from that of the second base layer.

Assignees

• Starck H C Inc

Inventors

• Jalili Helia
• Dary Francois
• Cox Barbara

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/032

  of conductive barrier, adhesion or liner layers · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10D86/40 Primary

  characterised by multiple TFTs · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title