Electronic devices having bilayer capping layers and/or barrier layers

US10558284B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10558284-B2
Application numberUS-201916512574-A
CountryUS
Kind codeB2
Filing dateJul 16, 2019
Priority dateJan 19, 2017
Publication dateFeb 11, 2020
Grant dateFeb 11, 2020

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

In various embodiments, electronic devices such as thin-film transistors and/or touch-panel displays incorporate bilayer capping layers and/or barrier layers.

First claim

Opening claim text (preview).

What is claimed is: 1. A touch-panel display comprising: a substrate; and an interconnect disposed over the substrate, wherein the interconnect comprises: (a) a bilayer barrier layer comprising a base layer and a dielectric layer disposed thereover, wherein (i) the base layer comprises an alloy of Cu and/or Mo with 0.5 weight %-50 weight % of one or more anodizable alloying elements selected from the list consisting of Ta, Nb, Al, Hf, Zr, Ti, and Mg, and (ii) the dielectric layer comprises an oxide, nitride, or oxynitride of the one or more anodizable alloying elements, and (b) disposed over the bilayer barrier layer, a conductor layer comprising at least one of Cu, Ag, Al, or Au. 2. The touch-panel display of claim 1 , further comprising: a plurality of conductive touch-panel row sensors (i) arranged in lines extending along a first direction and (ii) disposed over the substrate; and a plurality of conductive touch-panel column sensors (i) arranged in lines extending along a second direction and intersecting the lines of the row sensors and (ii) disposed over the substrate, wherein the interconnect (i) is disposed at a point of intersection between a line of row sensors and a line of column sensors, and (ii) electrically connects two column sensors or two row sensors. 3. The touch-panel display of claim 2 , wherein the interconnect extends over or under a row sensor and electrically connects two column sensors, and further comprising an insulating layer disposed between the interconnect and the row sensor and electrically insulating the interconnect and the row sensor. 4. The touch-panel display of claim 2 , wherein the interconnect extends over or under a column sensor and electrically connects two row sensors, and further comprising an insulating layer disposed between the interconnect and the column sensor and electrically insulating the interconnect and the column sensor. 5. The touch-panel display of claim 2 , wherein the row sensors and column sensors comprise a substantially transparent conductive material. 6. The touch-panel display of claim 5 , wherein the row sensors and column sensors comprise indium tin oxide. 7. The touch-panel display of claim 1 , wherein the substrate comprises an insulating material. 8. The touch-panel display of claim 1 , wherein the substrate comprises glass. 9. The touch-panel display of claim 1 , wherein the base layer comprises an alloy of (i) Mo and Nb, (ii) Mo, Ta, and Nb, (iii) Mo, Nb, and Ti, (iv) Mo and Ti, or (v) Mo, Nb, and Zr. 10. The touch-panel display of claim 1 , wherein the base layer comprises an alloy of Cu, Ta, and Zr. 11. The touch-panel display of claim 1 , wherein the dielectric layer is substantially free of Cu and/or Mo. 12. The touch-panel display of claim 1 , wherein the base layer comprises: an interfacial portion disposed beneath and in contact with the dielectric layer; and a bottom portion disposed beneath the interfacial portion. 13. The touch-panel display of claim 12 , wherein a concentration of at least one of the one or more anodizable alloying elements within the interfacial portion is less than a concentration of at least one of the one or more anodizable alloying elements within the bottom portion. 14. The touch-panel display of claim 12 , wherein the interfacial portion is substantially free of at least one of the one or more anodizable alloying elements. 15. The touch-panel display of claim 12 , wherein the interfacial portion is substantially free of all of said one or more anodizable alloying elements. 16. The touch-panel display of claim 1 , wherein the base layer comprises an alloy of Mo with 0.5 weight %-50 weight % of one or more anodizable alloying elements selected from the list consisting of Ta, Nb, Al, Hf, Zr, Ti, and Mg. 17. The touch-panel display of claim 1 , wherein the base layer comprises an alloy of Cu with 0.5 weight %-50 weight % of one or more anodizable alloying elements selected from the list consisting of Ta, Nb, Al, Hf, Zr, Ti, and Mg. 18. The touch-panel display of claim 1 , wherein the base layer comprises an alloy of Cu and Mo with 0.5 weight %-50 weight % of one or more anodizable alloying elements selected from the list consisting of Ta, Nb, Al, Hf, Zr, Ti, and Mg.

Assignees

Inventors

Classifications

  • Barrier, adhesion or liner layers · CPC title

  • of conductive barrier, adhesion or liner layers · CPC title

  • Input devices, e.g. touch panels · CPC title

  • Wiring, e.g. gate line, drain line · CPC title

  • G06F3/041Primary

    Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10558284B2 cover?
In various embodiments, electronic devices such as thin-film transistors and/or touch-panel displays incorporate bilayer capping layers and/or barrier layers.
Who is the assignee on this patent?
Starck H C Inc
What technology area does this patent fall under?
Primary CPC classification G06F3/041. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 11 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).