Three-dimensional semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-11587947-B2
Application number	US-202117355824-A
Country	US
Kind code	B2
Filing date	Jun 23, 2021
Priority date	Dec 12, 2018
Publication date	Feb 21, 2023
Grant date	Feb 21, 2023

Abstract

In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device, comprising:
a substrate including a cell array region and a connection region;
a stack structure disposed on the substrate and comprising a plurality of electrodes and first insulating layers disposed between the electrodes, the stack structure having a stair structure on the connection region;
a vertical channel structure penetrating the stack structure on the cell array region; and
a vertical dummy structure penetrating at least a portion of the stair structure on the connection region,
wherein the stack structure further comprises: a second insulating layer selectively disposed on the cell array region and not disposed on the connection region,
wherein a maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer,
wherein the vertical dummy structure includes a lower dummy structure and an upper dummy structure that vertically overlaps with the lower dummy structure, and
wherein the upper dummy structure is vertically spaced apart from the lower dummy structure.

2. The 3D semiconductor memory device of claim 1 , wherein a top surface of the lower dummy structure is lower than a top surface of the second insulating layer.

3. The 3D semiconductor memory device of claim 1 , wherein a bottom surface of the upper dummy structure is coplanar with a top surface of the second insulating layer.

4. The 3D semiconductor memory device of claim 1 , wherein the lower and upper dummy structures include silicon oxide, silicon nitride, silicon oxynitride, or poly-silicon.

5. The 3D semiconductor memory device of claim 1 , wherein a first electrode of the plurality of electrodes extends from a sidewall of the second insulating layer onto the connection region.

6. The 3D semiconductor memory device of claim 5 , wherein a top surface of the lower dummy structure is lower than a bottom surface of the first electrode.

7. The 3D semiconductor memory device of claim 1 , wherein the vertical channel structure and the vertical dummy structure include different layers.

8. The 3D semiconductor memory device of claim 1 , wherein the vertical channel structure and the vertical dummy structure include the same layers.

9. A three-dimensional (3D) semiconductor memory device, comprising:
a substrate including a cell array region and a connection region;
a stack structure disposed on the substrate and comprising: a lower structure disposed on the substrate; and an upper structure disposed on the lower structure, wherein each of the lower structure and the upper structure comprises: a plurality of stacked electrodes; and first insulating layers disposed between the electrodes;
a vertical channel structure penetrating the stack structure on the cell array region; and
a vertical dummy structure penetrating at least a portion of the stack structure on the connection region,
wherein the lower structure on the cell array region further comprises: a second insulating layer disposed on an uppermost portion thereof,
wherein the vertical dummy structure includes a lower dummy structure and an upper dummy structure that is vertically spaced apart from the lower dummy structure, and
wherein a top surface of the lower dummy structure is lower than a top surface of the second insulating layer.

10. The 3D semiconductor memory device of claim 9 , wherein the upper dummy structure vertically overlaps with the lower dummy structure.

11. The 3D semiconductor memory device of claim 9 , wherein a bottom surface of the upper dummy structure is coplanar with the top surface of the second insulating layer.

12. The 3D semiconductor memory device of claim 9 , wherein the lower and upper dummy structures include silicon oxide, silicon nitride, silicon oxynitride, or poly-silicon.

13. The 3D semiconductor memory device of claim 1 , wherein an uppermost electrode of the lower structure extends from a sidewall of the second insulating layer onto the connection region, and
wherein the top surface of the lower dummy structure is lower than a bottom surface of the uppermost electrode of the lower structure.

14. The 3D semiconductor memory device of claim 9 , wherein a height of the stack structure on the connection region decreases as a horizontal distance from the cell array region increases.

15. A three-dimensional (3D) semiconductor memory device, comprising:
a substrate including a cell array region and a connection region;
a stack structure disposed on the substrate and having a stair structure on the connection region, the stack structure comprising a plurality of electrodes stacked and spaced apart from each other;
a vertical channel structure penetrating the stack structure on the cell array region; and
a first vertical dummy structure and a second vertical dummy structure that penetrate the stair structure on the connection region,
wherein the second vertical dummy structure is closer to the cell array region than the first vertical dummy structure,
wherein each of the first and second vertical dummy structures includes a lower dummy structure and an upper dummy structure that vertically overlaps with the lower dummy structure,
wherein the upper dummy structure of the first vertical dummy structure is vertically spaced apart from the lower dummy structure of the first vertical dummy structure, and
wherein the upper dummy structure of the second vertical dummy structure is in contact with the lower dummy structure of the second vertical dummy structure.

16. The 3D semiconductor memory device of claim 15 , wherein a sidewall of the second vertical channel structure has a stepped profile.

17. The 3D semiconductor memory device of claim 15 , wherein a top surface of the lower dummy structure of the first vertical dummy structure is lower than a top surface of the lower dummy structure of the second vertical dummy structure.

18. The 3D semiconductor memory device of claim 15 , wherein a bottom surface of the upper dummy structure of the first vertical dummy structure is coplanar with a bottom surface of the upper dummy structure of the second vertical dummy structure.

19. The 3D semiconductor memory device of claim 15 , wherein the stack structure further comprises an insulating layer selectively disposed on the cell array region and not disposed on the connection region,
wherein a top surface of the lower dummy structure of the second vertical dummy structure is coplanar with a top surface of the insulating layer, and
wherein a top surface of the lower dummy structure of the first vertical dummy structure is lower than the top surface of the insulating layer.

20. The 3D semiconductor memory device of claim 15 , wherein the first and second vertical dummy structures comprise silicon oxide, silicon nitride, silicon oxynitride, or poly-silicon.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kang-Won
• Song Jaeyoung
• Lee Dong-Sik
• Jang Donghoon

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10B12/485 Primary

  Bit line contacts · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10B12/488

  Word lines · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title