Synchronization and order detection in a memory system

Patent metadata

Field	Value
Publication number	US-9430418-B2
Application number	US-201313835485-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

First claim

What is claimed is:

1. A system for out-of-synchronization and out-of-order detection in a memory system, the system comprising:
a plurality of channels each providing communication with a memory buffer chip and a plurality of memory devices; and
a memory control unit coupled to the plurality of channels, the memory control unit configured to perform a method comprising:
receiving frames on two or more of the channels;
identifying, by the memory control unit, an alignment logic input in each of the received frames;
generating, by the memory control unit, a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input, the summarized input comprising a combination of tag inputs and memory buffer chip multiple-input shift-register inputs that are separately selected using bit-wise ANDs to apply respective mask values;
adjusting, by the memory control unit, a timing alignment of the summarized input for each of the channels of the received frames based on a skew value per channel to adjust a relative timing between the tag inputs and the memory buffer chip multiple-input shift-register inputs per channel;
comparing each of the timing adjusted summarized inputs; and
based on a mismatch between at least two of the timing adjusted summarized inputs, asserting a miscompare signal by the memory control unit.

2. The system of claim 1 , wherein the tag inputs comprise a combination of a data tag and a done tag and the mismatch of the at least two of the timing adjusted summarized inputs based on one or more of the data tag and the done tag is detected as out-of-order, wherein the data tag corresponds to an assigned command tag returned from the memory buffer chip to correlate read data to an original read command and the done tag returned from the memory buffer chip indicates command completion.

3. The system of claim 1 , wherein generating the summarized input further comprises writing the alignment logic input to a multiple-input shift register and selecting a single bit output of the multiple-input shift register as the summarized input.

4. The system of claim 1 , wherein the memory control unit is further configured to perform the method comprising:
performing a bit-wise XOR on an output of the bit-wise ANDs in combination with a shifted value of a multiple-input shift register to update the multiple-input shift register per frame and generate the summarized input.

5. The system of claim 1 , wherein the alignment logic input comprises a multiple-input shift register value generated by one of the memory buffer chips, and the mismatch of the at least two of the timing adjusted summarized inputs based on the multiple-input shift register value generated by one of the memory buffer chips is detected as out-of-synchronization.

6. The system of claim 5 , wherein the multiple-input shift register value is derived from periodic refresh timer events, to determine that corresponding buffer refresh intervals are running synchronously with each other.

7. The system of claim 1 , wherein the memory control is further configured to perform the method comprising:
removing one of the channels from the comparing based on identifying that the channel is marked as failed.

8. A computer implemented method for out-of-synchronization and out-of-order detection in a memory system, the method comprising:
receiving frames on two or more channels of the memory system at a memory control unit;
identifying, by the memory control unit, an alignment logic input in each of the received frames;
generating, by the memory control unit, a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input, the summarized input comprising a combination of tag inputs and memory buffer chip multiple-input shift-register inputs that are separately selected using bit-wise ANDs to apply respective mask values;
adjusting, by the memory control unit, a timing alignment of the summarized input for each of the channels of the received frames based on a skew value per channel to adjust a relative timing between the tag inputs and the memory buffer chip multiple-input shift-register inputs per channel;
comparing each of the timing adjusted summarized inputs; and
based on a mismatch between at least two of the timing adjusted summarized inputs, asserting a miscompare signal by the memory control unit.

9. The method of claim 8 , wherein the tag inputs comprise a combination of a data tag and a done tag, and the mismatch of the at least two of the timing adjusted summarized inputs based on one or more of the data tag and the done tag is detected as out-of-order, wherein the data tag corresponds to an assigned command tag returned from the memory buffer chip to correlate read data to an original read command and the done tag returned from the memory buffer chip indicates command completion.

10. The method of claim 8 , wherein generating the summarized input further comprises writing the alignment logic input to a multiple-input shift register and selecting a single bit output of the multiple-input shift register as the summarized input.

11. The method of claim 8 , further comprising:
performing a bit-wise XOR on an output of the bit-wise ANDs in combination with a shifted value of a multiple-input shift register to update the multiple-input shift register per frame and generate the summarized input.

12. The method of claim 8 , wherein the alignment logic input comprises a multiple-input shift register value generated by one of a plurality of memory buffer chips, and the mismatch of the at least two of the timing adjusted summarized inputs based on the multiple-input shift register value generated by one of the memory buffer chips is detected as out-of-synchronization.

13. The method of claim 12 , further comprising the multiple-input shift register value being derived from periodic refresh timer events, to determine that corresponding buffer refresh intervals are running synchronously with each other.

14. The method of claim 8 , further comprising:
removing one of the channels from the comparing based on identifying that the channel is marked as failed.

15. A computer program product for out-of-synchronization and out-of-order detection in a memory system, the computer program product comprising:
a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
receiving frames on two or more channels of the memory system at a memory control unit;
identifying, by the memory control unit, an alignment logic input in each of the received frames;
generating, by the memory control unit, a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input, the summarized input comprising a combination of tag inputs and memory buffer chip multiple-input shift-register inputs that are separately selected using bit-wise ANDs to apply respective mask values;
adjusting, by the memory control unit, a timing alignment of the summarized input for each of the channels of the received frames based on a skew value per channel to adjust a relative timing between the tag inputs and the memory buffer chip multiple-input shift-register inputs per channel;
comparing each of the timing adjusted summarized inputs; and
based on a mismatch between at least two of the timing adjusted summarized inputs, asserting a miscompare signal by the memory control unit.

16. The computer program product of cl

Assignees

• IBM

Inventors

• Meaney Patrick J
• Gilda Glenn D
• Retter Eric E
• Dodson John S
• Van Huben Gary A
• Michael Brad W
• Powell Stephen J

Classifications

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F11/1679 Primary

  at clock signal level · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title