Multiple dies hardware processors and methods

Patent metadata

Field	Value
Publication number	US-11586579-B2
Application number	US-202117513795-A
Country	US
Kind code	B2
Filing date	Oct 28, 2021
Priority date	Oct 10, 2016
Publication date	Feb 21, 2023
Grant date	Feb 21, 2023

Abstract

Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

First claim

What is claimed is:

1. A processor comprising:
a multi-die package substrate;
a plurality of modular dies mounted on the multi-die package substrate and including a first die and a plurality of other dies;
a plurality of secondary management controllers, each secondary management controller integral to a corresponding one of the plurality of other dies;
an interconnect coupled to the plurality of modular dies; and
a primary management controller integral to the first die to transmit one or more management requests to the plurality of secondary management controllers over the interconnect, the plurality of secondary management controllers to perform a modification to a clock of the corresponding one of the plurality of other dies based, at least in part, on the one or more management requests.

2. The processor of claim 1 , wherein the plurality of secondary management controllers are to also perform a modification to a voltage of the corresponding one of the plurality of other dies based, at least in part, on the one or more management requests.

3. The processor of claim 1 , wherein the modification to the clock of the corresponding one of the plurality of other dies is a modification of an operating frequency of the clock of the corresponding one of the plurality of other dies.

4. The processor of claim 3 , wherein the modification to the clock of the corresponding one of the plurality of other dies further comprises a modification of a clock edge placement of the clock of the corresponding one of the plurality of other dies.

5. The processor of claim 1 , wherein the modification to the clock of the corresponding one of the plurality of other dies is a modification of a clock edge placement of the clock of the corresponding one of the plurality of other dies.

6. The processor of claim 1 , wherein the first die is a different design than at least one of the plurality of other dies.

7. The processor of claim 1 , wherein the first die is a mirror image of at least one of the plurality of other dies.

8. The processor of claim 1 , wherein the plurality of secondary management controllers is to cause a write of a control register of a locked loop circuit of the clock in the corresponding one of the plurality of other dies based, at least in part, on the one or more management requests.

9. A method comprising:
transmitting, over an interconnect coupled to a plurality of modular dies mounted on a multi-die package substrate and including a first die and a plurality of other dies, one or more management requests from a primary management controller integral with the first die to a plurality of secondary management controllers of the plurality of other dies, each secondary management controller integral with a corresponding one of the plurality of other dies; and
performing, by the plurality of secondary management controllers, a modification to a clock of the corresponding one of the plurality of other dies based, at least in part, on the one or more management requests.

10. The method of claim 9 , further comprising performing, by the plurality of secondary management controllers, a modification to a voltage of the corresponding one of the plurality of other dies based, at least in part, on the one or more management requests.

11. The method of claim 9 , wherein the modification to the clock of the corresponding one of the plurality of other dies is a modification of an operating frequency of the clock of the corresponding one of the plurality of other dies.

12. The method of claim 11 , wherein the modification to the clock of the corresponding one of the plurality of other dies further comprises a modification of a clock edge placement of the clock of the corresponding one of the plurality of other dies.

13. The method of claim 9 , wherein the modification to the clock of the corresponding one of the plurality of other dies is a modification of a clock edge placement of the clock of the corresponding one of the plurality of other dies.

14. The method of claim 9 , wherein the first die is a different design than at least one of the plurality of other dies.

15. The method of claim 9 , wherein the first die is a mirror image of at least one of the plurality of other dies.

16. The method of claim 9 , wherein the performing comprises causing, by the plurality of secondary management controllers, a write of a control register of a locked loop circuit of the clock in the corresponding one of the plurality of other dies based, at least in part, on the one or more management requests.

17. A processor comprising:
a multi-die package substrate;
a plurality of modular dies mounted on the multi-die package substrate and including a first die and a plurality of other dies, each of the plurality of modular dies comprising a corresponding intra-die interconnect;
a plurality of secondary management controllers, each secondary management controller integral to a corresponding one of the plurality of other dies;
an inter-die interconnect coupled to the intra-die interconnects of the plurality of modular dies; and
a primary management controller integral to the first die to transmit one or more management requests to the plurality of secondary management controllers over the intra-die interconnects and the inter-die interconnect, the plurality of secondary management controllers to perform a modification to a clock of the corresponding one of the plurality of other dies based, at least in part, on the one or more management requests.

18. The processor of claim 17 , wherein the plurality of secondary management controllers are to also perform a modification to a voltage of the corresponding one of the plurality of other dies based, at least in part, on the one or more management requests.

19. The processor of claim 17 , wherein the modification to the clock of the corresponding one of the plurality of other dies is a modification of an operating frequency of the clock of the corresponding one of the plurality of other dies.

20. The processor of claim 19 , wherein the modification to the clock of the corresponding one of the plurality of other dies further comprises a modification of a clock edge placement of the clock of the corresponding one of the plurality of other dies.

21. The processor of claim 17 , wherein the modification to the clock of the corresponding one of the plurality of other dies is a modification of a clock edge placement of the clock of the corresponding one of the plurality of other dies.

22. The processor of claim 17 , wherein the first die is a different design than at least one of the plurality of other dies.

23. The processor of claim 17 , wherein the first die is a mirror image of at least one of the plurality of other dies.

24. The processor of claim 17 , wherein the plurality of secondary management controllers is to cause a write of a control register of a locked loop circuit of the clock in the corresponding one of the plurality of other dies based, at least in part, on the one or more management requests.

Assignees

• Intel Corp

Inventors

• Nassif Nevine
• Liu Yen-Cheng
• Sistla Krishnakanth V
• Pasdast Gerald
• Eachempati Siva Soumya
• Singh Tejpal
• Varma Ankush
• Kumashikar Mahesh K
• Nimmagadda Srikanth
• Molnar Carleton L
• Geetha Vedaraman
• Chamberlain Jeffrey D
• Halleck William R
• Chrysos George Z
• Ayers John R
• Subbareddy Dheeraj R

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F9/3869

  Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking · CPC title

• G06F15/167

  using a common memory, e.g. mailbox · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title