Multiple dies hardware processors and methods

Patent metadata

Field	Value
Publication number	US-10795853-B2
Application number	US-201715721822-A
Country	US
Kind code	B2
Filing date	Sep 30, 2017
Priority date	Oct 10, 2016
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

First claim

What is claimed is:

1. A hardware processor comprising:
a plurality of physically separate dies;
an interconnect to electrically couple the plurality of physically separate dies together;
a first transmitter circuit of a first die of the plurality of physically separate dies;
a second receiver circuit of a second die of the plurality of physically separate dies electrically coupled to the first transmitter circuit of the first die through at least one data lane of the interconnect that corresponds to a clock lane of the interconnect; and
a clock circuit to receive a request from the first transmitter circuit to change the second receiver circuit to an operating frequency and a clocking rate for the operating frequency, cause a look-up in a data storage device of a predetermined clock phase placement for the operating frequency and the clocking rate for the operating frequency from a plurality of predetermined clock phase placements for a first clocking rate for each single frequency of different operating frequencies and for a second, different clocking rate for each single frequency of different operating frequencies, and cause the second receiver circuit to receive data from the first transmitter circuit on the at least one data lane with the predetermined clock phase placement for the operating frequency and the clocking rate for the operating frequency on the clock lane.

2. The hardware processor of claim 1 , wherein both a leading-edge placement and a trailing-edge placement of a predetermined clock phase placement for a first clocking rate of the operating frequency are different than a leading-edge placement and a trailing-edge placement of a predetermined clock phase placement for a predetermined clock phase placement for a second, different clocking rate of the operating frequency.

3. The hardware processor of claim 1 , wherein the clock circuit is to switch to a closed-loop mode that adjusts the operating frequency after the clock circuit is updated with the predetermined clock phase placement for the operating frequency and the clocking rate for the operating frequency in an open-loop mode.

4. The hardware processor of claim 1 , wherein each physically separate die is identical.

5. The hardware processor of claim 1 , further comprising a cache coherency circuit to manage a first cache of one of the plurality of physically separate dies and a second cache of another of the plurality of physically separate dies in a single cache coherency domain.

6. The hardware processor of claim 1 , further comprising a cache coherency circuit to manage a cache in each of the plurality of physically separate dies in a single cache coherency domain.

7. The hardware processor of claim 1 , wherein cache coherency circuitry in each of the plurality of physically separate dies is switchable between a master mode and a slave mode.

8. The hardware processor of claim 1 , wherein a first die and a second die of the plurality of physically separate dies extend in a single plane and a third die of the plurality of physically separate dies is laterally spaced from that single plane.

9. A method comprising:
electrically coupling a plurality of physically separate dies together with an interconnect with a first transmitter circuit of a first die of the plurality of physically separate dies electrically coupled to a second receiver circuit of a second die of the plurality of physically separate dies through at least one data lane of the interconnect that corresponds to a clock lane of the interconnect;
receiving a request from the first transmitter circuit to change the second receiver circuit to an operating frequency and a clocking rate for the operating frequency;
performing a look-up in a data storage device of a predetermined clock phase placement for the operating frequency and the clocking rate for the operating frequency from a plurality of predetermined clock phase placements for a first clocking rate for each single frequency of different operating frequencies and for a second, different clocking rate for each single frequency of different operating frequencies; and
receiving data with the second receiver circuit from the first transmitter circuit on the at least one data lane with the predetermined clock phase placement for the operating frequency and the clocking rate for the operating frequency on the clock lane.

10. The method of claim 9 , wherein both a leading-edge placement and a trailing-edge placement of a predetermined clock phase placement for a first clocking rate of the operating frequency are different than a leading-edge placement and a trailing-edge placement of a predetermined clock phase placement for a predetermined clock phase placement for a second, different clocking rate of the operating frequency.

11. The method of claim 9 , further comprising switching to a closed-loop mode that adjusts the operating frequency after a clock circuit is updated with the predetermined clock phase placement for the operating frequency and the clocking rate for the operating frequency in an open-loop mode.

12. The method of claim 9 , wherein the first die and the second die are identical, physically separate dies.

13. The method of claim 9 , further comprising providing a cache coherency circuit to manage a first cache of one of the plurality of physically separate dies and a second cache of another of the plurality of physically separate dies in a single cache coherency domain.

14. The method of claim 9 , further comprising providing a cache coherency circuit to manage a cache in each of the plurality of physically separate dies in a single cache coherency domain.

15. The method of claim 9 , further comprising providing cache coherency circuitry in each of the plurality of physically separate dies that is switchable between a master mode and a slave mode.

16. The method of claim 9 , further comprising affixing a first die and a second die of the plurality of physically separate dies in a single plane and affixing a third die of the plurality of physically separate dies in a laterally spaced orientation from that single plane.

17. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
electrically coupling a plurality of physically separate dies together with an interconnect with a first transmitter circuit of a first die of the plurality of physically separate dies electrically coupled to a second receiver circuit of a second die of the plurality of physically separate dies through at least one data lane of the interconnect that corresponds to a clock lane of the interconnect;
receiving a request from the first transmitter circuit to change the second receiver circuit to an operating frequency and a clocking rate for the operating frequency;
performing a look-up in a data storage device of a predetermined clock phase placement for the operating frequency and the clocking rate for the operating frequency from a plurality of predetermined clock phase placements for a first clocking rate for each single frequency of different operating frequencies and for a second, different clocking rate for each single frequency of different operating frequencies; and
receiving data with the second receiver circuit from the first transmitter circuit on the at least one data lane with the predetermined clock phase placement for the operating frequency and the clocking rate for the operating frequency on the clock lane.

18. The non-transitory machine readable medium of claim 17 , wherein both a leadi

Assignees

• Intel Corp

Inventors

• Nassif Nevine
• Liu Yen-Cheng
• Sistla Krishnakanth V
• Pasdast Gerald
• Eachempati Siva Soumya
• Singh Tejpal
• Varma Ankush
• Kumashikar Mahesh K
• Nimmagadda Srikanth
• Molnar Carleton L
• Geetha Vedaraman
• Chamberlain Jeffrey D
• Halleck William R
• Chrysos George Z
• Ayers John R
• Subbareddy Dheeraj R

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• G06F15/7889 Primary

  Reconfigurable logic implemented as a co-processor (instruction execution using a coprocessor G06F9/3877) · CPC title

• G06F15/17312 Primary

  Routing techniques specific to parallel machines, e.g. wormhole, store and forward, shortest path problem congestion (routing on a LAN H04L45/00) · CPC title