Through-hole and surface mount printed circuit card connections for improved power component soldering

Patent metadata

Field	Value
Publication number	US-11570894-B2
Application number	US-202117319479-A
Country	US
Kind code	B2
Filing date	May 13, 2021
Priority date	May 15, 2020
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

A system of circuit card components each include through-holes for soldering having recessed copper layers for thermal insulation. Thermal insulation prevents heat conduction away from flowing solder, allowing the solder to flow freely through the through-hole. Even high-temperature, lead-free solders may maintain the necessary temperature to flow. Different circuit layers include specialized features based on distance from a top or bottom surface. Vias surrounding the through-hole maintain the necessary cross-sectional area for electrical connectivity.

First claim

What is claimed is:

1. A circuit card layer comprising:
a non-conductive core; and
a conductive layer disposed on the non-conductive core,
wherein:
the circuit card layer comprises internal ground plane portions defining a return path;
the circuit card layer defines a surface mount proximal region;
the circuit card layer defines a plurality of vias disposed regularly around the surface mount proximal region;
the circuit card layer defines a cross-pattern of traces connecting the plurality of vias and the surface mount proximal region; and
the conductive layer is set back from the cross-pattern of traces to reduce thermal conduction from a surface mounted connector to the conductive layer during a soldering operation.

2. The circuit card layer of claim 1 , wherein the conductive layer is set back at least twenty thousandths of an inch (20 mil) from the surface mount proximal region.

3. The circuit card layer of claim 1 , wherein the circuit card layer comprises a coplanar connection layer of a circuit card.

4. A circuit card comprising:
a plurality of circuit card layers, each of the plurality of circuit card layers comprising:
a non-conductive core; and
a conductive layer disposed on the non-conductive core; and

a plurality of vias, each of the plurality of vias intersecting each of the plurality of circuit card layers in a corresponding conductive layer,
wherein:
each of the plurality of circuit card layers defines a through-hole configured for receiving a through-hole pin;
each conductive layer is set back from the corresponding through-hole to insulate a through-hole pin during a soldering operation;
the plurality of vias are disposed regularly around the through-hole;
at least one of the plurality of circuit card layers comprises an internal ground plane layer defining a return path, the conductive layer of the internal ground plane layer is set back from the corresponding through-hole and from each of the plurality of vias, in a single contiguous region; and
at least one of the plurality of circuit card layers comprises a top through-hole connection layer disposed at a top surface of the circuit card, the top through-hole connection layer comprising a cross-pattern of traces connecting the top through-hole connection layer to the plurality of vias, the conductive layer of the top through-hole layer being setback from the cross-pattern of traces.

5. The circuit card of claim 4 , wherein the through-hole hole is physically connected only to the conductive layer of the top through-hole connection layer.

6. The circuit card of claim 4 , further comprising: a bottom through-hole connection layer disposed at a bottom surface of the circuit card, wherein the bottom through-hole connection layer comprises a plurality of traces connecting the bottom through-hole connection layer to the plurality of vias.

7. The circuit card of claim 6 , wherein the through-hole hole is electrically connected only to the conductive layers of the top through-hole connection layer and the bottom through-hole connection layer.

8. The circuit card of claim 4 , wherein:
a first circuit card layer in the plurality of circuit card layers comprises an upper outer ground layer; and
a second circuit card layer in the plurality of circuit card layers comprises a lower outer ground layer.

9. The circuit card of claim 4 , wherein:
a first circuit card layer in the plurality of circuit card layers comprises an upper coplanar connection layer; and
a second circuit card layer in the plurality of circuit card layers comprises a lower coplanar connection layer.

Assignees

• Rockwell Collins Inc

Inventors

• Mayfield James B
• Campbell Robert P
• Deloy Jeffrey J
• Bauer John A

Classifications

• H05K2201/09609

  Via grid, i.e. two-dimensional array of vias or holes in a single plane · CPC title

• H05K1/0298

  Multilayer circuits · CPC title

• H05K2201/1031

  Surface mounted metallic connector elements · CPC title

• H05K2201/10303

  Pin-in-hole mounted pins · CPC title

• H05K1/116 Primary

  Lands, clearance holes or other lay-out details concerning the surrounding of a via · CPC title