Printed circuit board and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9942985-B2
Application number	US-201514627319-A
Country	US
Kind code	B2
Filing date	Feb 20, 2015
Priority date	Feb 21, 2014
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

Disclosed is a printed circuit board including a base insulating layer, an upper insulating layer formed on the base insulating layer, a lower insulating layer formed under the base insulating layer. The upper insulating layer has a plurality of first vias filled in the first through holes, respectively, and the lower insulating layer has a second via filled in one second through hole formed through a top and a bottom surface and commonly connected with the first vias.

First claim

What is claimed is:

1. A printed circuit board comprising:
a base insulating layer;
an upper insulating layer formed on the base insulating layer and having a plurality of first through holes spaced apart from each other in a horizontal direction;
a lower insulating layer formed under the base insulating layer and having a second through hole formed in a region overlapped with the first through holes;
a single first circuit pattern interposed between the base insulating layer and the lower insulating layer,
a plurality of second circuit patterns interposed between the base insulating layer and the upper insulating layer and spaced apart from each other in the horizontal direction,
a first electronic device attached to the upper insulating layer;
a plurality of connection parts to electrically connect a chip connector formed at the first electronic device with the first vias formed in the upper insulating layer, respectively, and
a second electronic device embedded in the base insulating layer,
wherein the plurality of the connection parts are spaced apart from each other in a horizontal direction,
wherein the upper insulating layer has a plurality of first vias filled in the first through holes, respectively,
wherein the lower insulating layer has a single second via filled in the second through hole and commonly connected with the first vias,
wherein the base insulating layer has a plurality of third through holes spaced apart from each other in the horizontal direction, and a plurality of third vias filled in the third through holes, respectively,
wherein each of the third vias comprises:
a plurality of first via parts formed in the base insulating layer and connected with a top surface of the second electronic device, and spaced apart from each other in the horizontal direction; and
a plurality of second via parts formed in the base insulating layer and connected with a bottom surface of the second electronic device, and spaced apart from each other in the horizontal direction,
wherein first via parts of the third vias are connected with the first vias formed in the upper insulating layer, respectively, and second via parts of the third vias are commonly connected with one second via formed in the lower insulating layer,
wherein a top surface of the single second via is overlapped with bottom surfaces of the first vias in the horizontal direction,
wherein each of the third vias is connected with each of the first vias formed in the upper insulating layer,
wherein the single second via is commonly connected with the third vias,
wherein the single first circuit pattern has a top surface commonly making contact with bottom surfaces of the third vias and a bottom surface making contact with a top surface of the single second via,
wherein each of the second circuit patterns has a top surface making contact with one of the first vias and a bottom surface making contact with one of the third vias, and
wherein the top surface of the single first circuit pattern is overlapped with bottom surfaces of the second circuit patterns in the horizontal direction, and
wherein the plurality of the first through holes are separated from each other in a horizontal direction, and
wherein the plurality of the connection parts are separated from each other in a horizontal direction.

2. The printed circuit board of claim 1 , wherein the second via has a width wider than a sum of widths of the first vias.

3. The printed circuit board of claim 1 , wherein the lower insulating layer comprises:
a first lower insulating layer under the base insulating layer; and
a second lower insulating layer under the first lower insulating layer, and
wherein the first lower insulating layer has a third via part constituting an upper structure of the second via, and
the second lower insulating layer has a fourth via part constituting a lower structure of the second via.

4. The printed circuit board of claim 1 , wherein the single first circuit pattern has a width wider than a sum of widths of the plurality of second circuit patterns.

5. The printed circuit board of claim 3 , wherein the third and fourth via parts of the second via have one of a pyramid shape having a width gradually increased toward a lower portion from an upper portion thereof or a rod shape having equal upper and lower widths.

6. A method of fabricating a printed circuit board, the method comprising:
providing a base insulating layer;
forming an upper insulating layer having a plurality of first through holes on the base insulating layer, wherein the first through holes are spaced apart from each other in a horizontal direction;
forming a lower insulating layer, which is formed therein with a second through hole having a width wider than a width of each of the first through holes, under the base insulating layer;
forming a plurality of first vias by filling a metallic material in the first through holes;
forming a single second via by filling a metallic material in the second through hole;
forming a single first circuit pattern interposed between the base insulating layer and the lower insulating layer;
forming a plurality of second circuit pattern formed between the base insulating layer and the upper insulating layer,
wherein a region of the lower insulating layer, in which the second through hole is formed, is overlapped with a region of the upper insulating layer in which the first through holes are formed;
attaching a first electronic device to the upper insulating layer;
forming a plurality of connection parts to electrically connect a chip connector formed at the first electronic device with the first vias formed in the upper insulating layer, respectively;
embedding a second electronic device in the base insulating layer,
wherein the base insulating layer has a plurality of third through holes spaced apart from each in out in the horizontal direction and a plurality of third vias filled in the third through holes, respectively,
wherein a top surface of the single second via is overlapped with bottom surfaces of the first vias in the horizontal direction,
wherein the second via is commonly connected with the first vias,
wherein each of the third vias is connected with each of the first vias formed in the upper insulating layer,
wherein the single second via is commonly connected with the third vias,
wherein the single first circuit pattern has a top surface commonly making contact with bottom surfaces of the third vias and a bottom surface making contact with a top surface of the single second via,
wherein each of the second circuit patterns has a top surface making contact with one of the first vias and a bottom surface making contact with one of the third vias, and
wherein the top surface of the single first circuit pattern is overlapped with bottom surfaces of the second circuit patterns in the horizontal direction,
wherein the plurality of the connection parts are spaced apart from each other in a horizontal direction,
wherein each of the third vias comprises:
a plurality of first via parts formed in the base insulating layer and connected with a top surface of the second electronic device, and spaced apart from each other in the horizontal direction; and
a plurality of second via parts formed in the base insulating layer and connected with a bottom surface of the second electronic device, and spaced apart from each other in the horizontal direction,
wherein first via parts of the third vias are connected with the first vias formed in the upper insulating layer, respectively, and second via parts of the third vias are commonly connected with one second via formed in the lower insulating layer,

wherein the plurality of second circuit patterns are separated from each other in the horizonta

Assignees

• Lg Innotek Co Ltd

Inventors

• Shin Seung Yul
• Kim Jae Hwa
• Park Chung Sik
• Choi Chul

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W40/228 Primary

  the projecting parts being wire-shaped or pin-shaped · CPC title