Memory device, a memory system and an operating method of the memory device
US-12073914-B2 · Aug 27, 2024 · US
US2016141013A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016141013-A1 |
| Application number | US-201514672787-A |
| Country | US |
| Kind code | A1 |
| Filing date | Mar 30, 2015 |
| Priority date | Nov 14, 2014 |
| Publication date | May 19, 2016 |
| Grant date | — |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
An apparatus for controlling memory includes a memory controller, and a data interface that interfaces with and is in data communication with data lines, each having inherent skew. Each data line carries a data signal. The data lines connect the memory controller to the memory. The apparatus also includes data de-skewers, each associated with a corresponding data line, a strobe interface that interfaces with a strobe line that connects the memory controller to the memory and that applies a timing signal to the strobe line, and a strobe de-skewer connected to the strobe line. Each data de-skewer operates in read or write mode. A particular data line's data de-skewer applies a compensation skew to a data signal carried by that line.
Opening claim text (preview).
Having described the invention, and a preferred embodiment thereof, what is claimed as new, and secured by letters patent is: 1 . An apparatus for controlling a memory, said apparatus comprising: a memory controller, a data interface that interfaces with data lines that connect said memory controller to said memory, a plurality of data de-skewers, each of said data de-skewers being associated with a corresponding one of said data lines, a strobe interface that interfaces with a strobe line that connects said memory controller to said memory, and a strobe de-skewer that is in communication with said strobe line, wherein each of said data lines carries a data signal, wherein said data interface is in data communication with each of said data lines, wherein said strobe interface is configured to apply a timing signal to said strobe line, wherein each of said data de-skewers is configured to operate in a write mode, in which a bit is to be written to said memory, and in a read mode, in which a bit is to be read from said memory, wherein said data de-skewer that corresponds to said data line is configured to apply a compensation skew to a data signal that is carried by said data line, wherein when said data de-skewer is being operated in said write mode, said data signal represents a bit that is to be written to said memory, and wherein when said data de-skewer is being operated in said read mode, said data signal represents a bit that has been read from said memory, wherein each of said data lines has an inherent skew, wherein each of said data de-skewers applies a compensation-skew to a data signal that is being carried by a data line with which said data de-skewer corresponds, and wherein said strobe de-skewer is configured to skew said timing signal by an amount that is selected to be one of less than and equal to a maximum delay of said strobe de-skewer and one of greater than and equal to a minimum delay of said strobe de-skewer. 2 . The apparatus of claim 1 , wherein said strobe de-skewer is configured to skew said timing signal by a timing-signal skew that depends at least in part on said inherent skews. 3 . The apparatus of claim 1 , wherein said strobe de-skewer is configured to skew said timing signal by a timing-signal skew selected to be as close as possible to one half of a difference between said maximum delay of said de-skewer and said minimum delay of said de-skewer. 4 . The apparatus of claim 1 , wherein said strobe de-skewer is configured to skew said timing signal by a timing-signal skew selected to be equal to one half of a difference between said maximum delay of said strobe de-skewer and said minimum delay of said strobe de-skewer. 5 . The apparatus of claim 1 , wherein said data lines comprise a first data line, wherein said first data line comprises a first data de-skewer, wherein said first data de-skewer defines a first observation window, wherein said first data line carries a first data signal, wherein said first data signal has a first data-valid window, and wherein said strobe de-skewer is configured to skew said timing signal by a timing-signal skew that has been selected based at least in part on an extent to which said first data-valid window extends into said first observation window. 6 . The apparatus of claim 1 , wherein said strobe de-skewer is configured to skew said timing signal by a timing-signal skew that has been selected to reduce a collective sampling error, wherein said data lines comprise a first data line and a second data line, wherein said first data line carries a first data signal, wherein said first data signal has a first data-valid window, wherein said first data-valid window has a first data-valid-window center, wherein said first data line is sampled at a first sample point, wherein a distance between said first sample point and said first data-valid-window center defines a first offset, wherein said second data line carries a second data signal, wherein said second data signal has a second data-valid window, wherein said second data-valid window has a second data-valid-window center, wherein said second data line is sampled at a second sample point, wherein a distance between said second sample point and said second data-valid-window center defines a second offset, and wherein said collective sampling error is a function of an extent to which each of said data signals is sampled at a center of a data-valid window thereof. 7 . The apparatus of claim 1 , wherein said strobe de-skewer is configured to skew said timing signal by a timing-signal skew that has been selected based at least in part on said compensation-skews applied to each of said data signals by said data de-skewers. 8 . The apparatus of claim 1 , wherein said strobe de-skewer is configured to skew said timing signal by a timing-signal skew that has been selected based at least in part on a failure to detect an edge, wherein said edge is an edge that is selected from the group consisting of a trailing edge of a data signal, and a leading edge of said data signal. 9 . The apparatus of claim 1 , wherein said strobe de-skewer is configured to skew said timing signal by a timing-signal skew that has been selected based at least in part on a particular set of compensation skews that have been selected for said data de-skewers, wherein said particular set of skews that have been selected for said data de-skewers were selected to cause each data signal to be sampled as closely as possible to a first delay stage of a data de-skewer associated with said data signal subject to the constraint that no data signal be skewed far enough to cause a data-valid window thereof to leave an observation window of a data de-skewer. 10 . A method of controlling a memory, said method comprising: receiving a plurality of data signals on corresponding data lines, each of which has an inherent skew, selecting compensation skews, each of which corresponds to one of said data lines, applying each of said compensation skews to a data signal that is being carried by a corresponding one of said data lines, wherein said data signal is a bit that has been read from said data line when operating in a read mode, and wherein said data signal is a bit that is to be written to said data line when operating in a write mode, from a range that extends from a maximum delay of a strobe de-skewer to a minimum delay of said strobe de-skewer, selecting a timing-signal skew to apply to said timing signal, and skewing said timing signal by said timing-signal skew. 11 . The method of claim 10 , wherein selecting a timing-signal skew to apply to said timing signal comprises selecting a timing-signal skew that depends at least in part on said inherent skews. 12 . The method of claim 10 , wherein selecting a timing-signal skew to apply to said timing signal comprises selecting a timing-signal skew to be as close as possible to one half of a difference between said maximum delay of said de-skewer and said minimum delay of said de-skewer. 13 . The method of claim 1 , wherein selecting a timing-signal skew to apply to said timing signal comprises selecting a timing-signal skew to be equal to one half of a difference between said maximum delay of said strobe de-skewer and said minimum delay of said strobe de-skewer. 14 . The method of claim 10 , wherein selecting a timing-signal skew to apply to said timing signal comprises selecting said timing-signal skew based at least in part on an extent to which a first data-valid window of a first data signal from said plurality of data signals extends into a first observation window of a first data de-skewer on a data line that carries said f
Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title
in clock generator or timing circuitry · CPC title
Output synchronization · CPC title
with adaption or trimming of parameters · CPC title
Input synchronization · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.