Semiconductor device with polygonal inductive device

Patent metadata

Field	Value
Publication number	US-11569164-B2
Application number	US-202016880336-A
Country	US
Kind code	B2
Filing date	May 21, 2020
Priority date	Nov 30, 2017
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
an inductive device, disposed over the semiconductor substrate; and
a conductive pattern, disposed between the semiconductor substrate and the inductive device, and comprising:
a first metal line, disposed in a first layer on the semiconductor substrate;
a second metal line, disposed in the first layer and separated from the first metal line, wherein the second metal line is arranged to be orthogonal to the first metal line, and a first terminal of the first metal line is proximal to a second terminal of the second metal line; and
a third metal line, disposed in a second layer on the semiconductor substrate and electrically connecting the first metal line to the second metal line,
wherein the first layer and the second layer are at different elevations, and the third metal line is disposed between the first terminal of the first metal line and the second terminal of the second metal line from a top view perspective.

2. The semiconductor device of claim 1 , further comprising:
a first conductive via, arranged to electrically connect the first metal line to the third metal line;
a second conductive via, arranged to electrically connect the second metal line to the third metal line.

3. The semiconductor device of claim 2 , wherein the first terminal of the first metal line is in contact with the first conductive via.

4. The semiconductor device of claim 2 , wherein the second terminal of the second metal line is in contact with the second conductive via.

5. The semiconductor device of claim 1 , further comprising:
a fourth metal line, disposed on the first layer;
a third conductive via, arranged to electrically connect the third metal line to the fourth metal line.

6. The semiconductor device of claim 5 , wherein the fourth metal line is orthogonal to the third metal line from the top perspective.

7. The semiconductor device of claim 1 , further comprising:
a fifth metal line, disposed on the first layer;
a sixth metal line, disposed on the first layer;
a seventh metal line, disposed on the second layer;
a fourth conductive via, arranged to electrically connect the fifth metal line to the seventh metal line;
a fifth conductive via, arranged to electrically connect the sixth metal line to the seventh metal line,
wherein the fifth metal line, the sixth metal line and the seventh metal line are arranged to be a straight line from the top perspective.

8. The semiconductor device of claim 7 , wherein the fifth metal line is orthogonal to the sixth metal line.

9. The semiconductor device of claim 7 , wherein the seventh metal line is parallel to the third metal line.

10. The semiconductor device of claim 7 , further comprising:
a fourth metal line, disposed on the first layer;
a third conductive via, arranged to electrically connect the third metal line to the fourth metal line,

wherein the seventh metal line is orthogonal to the fourth metal line.

11. The semiconductor device of claim 1 , wherein the inductive device includes a first line portion and a second line portion, the first line portion is orthogonal to the first metal line from the top perspective, and the second line portion is orthogonal to the second metal line from the top perspective.

12. A semiconductor device, comprising:
a substrate;
a first conductive line, disposed on a first layer on the substrate and extending along a first direction;
a second conductive line, disposed on the first layer and extending along a second direction orthogonal to the first direction;
a plurality of third conductive lines, disposed on a second layer on the substrate different from the first layer and disposed along the second direction, wherein each of the plurality of third conductive lines is orthogonal to and overlaps the first conductive line;
a plurality of first conductive vias, arranged to electrically connect the first conductive line to the plurality of third conductive lines; and
a plurality of fourth conductive lines, disposed on the second layer and separated from the plurality of third conductive lines, wherein each of the plurality of fourth conductive lines is orthogonal to and overlaps the second conductive line, wherein each of the plurality of third conductive lines is orthogonal to each of the plurality of fourth conductive lines.

13. The semiconductor device of claim 12 , further comprising:
a plurality of second conductive vias, arranged to electrically connect the second conductive line to the plurality of fourth conductive lines.

14. The semiconductor device of claim 13 , wherein one of the plurality of first conductive vias is arranged to electrically connect the first conductive line to the second conductive line.

15. The semiconductor device of claim 13 , wherein each of the plurality of first conductive vias extends between the first layer and the second layer.

16. The semiconductor device of claim 12 , wherein the plurality of fourth conductive lines are disposed along the first direction.

17. A semiconductor device, comprising:
a substrate;
a first conductive line, disposed on a first layer on the substrate, and designed to be a first direction;
a second conductive line, disposed on the first layer, and designed to be a second direction orthogonal to the first direction;
a plurality of third conductive lines, disposed on the first layer, and designed to be a third direction different form the first direction and the second direction, wherein the first conductive line, the second conductive line and the plurality of third conductive lines are separated from one another on the first layer; and
a plurality of fourth conductive lines, disposed on a second layer on the substrate different from the first layer, and designed to be the second direction orthogonal to the first direction,

wherein each of the plurality of third conductive lines is electrically connected to the first conductive line through the plurality of fourth conductive lines respectively.

18. The semiconductor device of claim 17 , further comprising a plurality of first conductive vias, arranged to electrically connect the first conductive line to the plurality of fourth conductive lines.

19. The semiconductor device of claim 18 , wherein each of the plurality of first conductive vias extends between the first layer and the second layer of the substrate.

20. The semiconductor device of claim 17 , wherein the plurality of third conductive lines are electrically coupled with the plurality of fourth conductive lines respectively.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Wen-Sheng
• Lo An-Hsun
• Yeh En-Hsiang
• Yeh Tzu-Jin

Classifications

• H01L28/10

  Electricity · mapped topic

• H01L23/5226 Primary

  Electricity · mapped topic

• H01L23/5227

  Electricity · mapped topic

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title