Dual-mode wireless charging device

Patent metadata

Field	Value
Publication number	US-10497646-B2
Application number	US-201615222815-A
Country	US
Kind code	B2
Filing date	Jul 28, 2016
Priority date	Jul 28, 2016
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

A semiconductor device includes a first molding layer; a second molding layer formed over the first molding layer; a first conductive coil including a first portion continuously formed in the first molding layer and a second portion continuously formed in the second molding layer, wherein the first and the second portions are laterally displaced from each other; and a second conductive coil formed in the second molding layer, wherein the second conductive coil is interweaved with the second portion of the first conductive coil in the second molding layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first molding layer;
a second molding layer formed over the first molding layer;
a first dielectric layer disposed between the first and second molding layers;
a first conductive coil including a first portion continuously formed in the first molding layer and a second portion continuously formed in the second molding layer;
a second conductive coil formed in the second molding layer, wherein the second conductive coil is interweaved with the second portion of the first conductive coil in the second molding layer;
at least one first via extending across at least a portion of the first dielectric layer from the second molding layer toward the first molding layer;
at least one redistribution line (RDL) disposed in the first dielectric layer and electrically coupled to the at least one first via, wherein the at least one first via and the at least one RDL electrically couple the first portion with the second portion such that the first and second portions are laterally offset from one another; and
an integrated circuit die formed in the second molding layer and electrically coupled to the second conductive coil.

2. The device of claim 1 , wherein the first portion of the first conductive coil includes a plurality of second vias extending through the first molding layer.

3. The device of claim 2 , wherein the second portion of the first conductive coil includes a plurality of third vias extending through the second molding layer.

4. The device of claim 3 , further comprising:
a second dielectric layer disposed between the first dielectric layer and the first molding layer; and
at least one fourth via disposed in the second dielectric layer and electrically coupling the at least one RDL with the first portion of the first conductive coil, wherein the at least one RDL is laterally disposed between the at least one first via and the at least one fourth via.

5. The device of claim 4 , wherein the second conductive coil includes a plurality of fifth vias that are disposed between the plurality of third vias of the first conductive coil in the second molding layer.

6. The device of claim 5 , wherein the plurality of fifth vias of the second conductive coil and the plurality of third vias of the first conductive coil are spaced from one another.

7. The device of claim 6 , wherein the plurality of fifth vias of the second conductive coil and at least one of the plurality of third vias of the first conductive coil are electrically formed as a capacitor.

8. The device of claim 7 , wherein a first inductor is defined by the first conductive coil, and a second inductor is defined by the second conductive coil.

9. The device of claim 8 , wherein the first inductor, the second inductor, and the capacitor are formed as a loop antenna of the device while the first inductor, the second inductor, and the capacitor are each operated at a resonant frequency.

10. The device of claim 9 , wherein the resonant frequency is defined by inductance values of the first and second inductors and a capacitance value of the capacitor.

11. A semiconductor device, comprising:
a first molding layer;
a second molding layer formed over the first molding layer;
a first dielectric layer disposed between the first and second molding layers;
a first conductive coil including a first portion continuously formed in the first molding layer and a second portion continuously formed in the second molding layer, wherein the first and the second portions are electrically coupled to each other;
a second conductive coil formed in the second molding layer, wherein the second conductive coil is interweaved with the second portion of the first conductive coil in the second molding layer; and
at least one first via extending across at least a portion of the first dielectric layer from the second molding layer toward the first molding layer;
at least one conductive line disposed in the first dielectric layer and electrically coupled to the at least one first via, wherein the at least one first via and the at least one conductive line electrically couple the first portion with the second portion such that the first and second portions are laterally offset from one another; and
an integrated circuit die formed in the second molding layer and electrically coupled to the second conductive coil.

12. The device of claim 11 , wherein the first portion of the first conductive coil includes a plurality of second vias extending through the first molding layer.

13. The device of claim 12 , wherein the second portion of the first conductive coil includes a plurality of third vias extending through the second molding layer.

14. The device of claim 13 , wherein the second conductive coil includes a plurality of fourth vias disposed substantially adjacent to the plurality of third vias of the first conductive coil in the second molding layer.

15. The device of claim 14 , wherein at least a portion of the plurality of fourth vias of the second conductive coil and at least a portion of the plurality of third vias of the first conductive coil are spaced from one another with portions of the second molding layer disposed therebetween so as to form a capacitor.

16. The device of claim 15 , wherein at least the plurality of fourth vias of the second conductive coil, the plurality of third vias of the first conductive coil, and the capacitor form a loop antenna of the device.

17. The device of claim 11 , wherein the first conductive coil forms a magnetically resonant inductor of the device.

18. The device of claim 11 , wherein the conductive line includes a redistribution line (RDL).

19. A semiconductor device, comprising:
a first molding layer;
a second molding layer formed over the first molding layer;
a first dielectric layer disposed between the first and second molding layers;
a first conductive coil including a first portion continuously formed in the first molding layer and a second portion continuously formed in the second molding layer;
a second conductive coil formed in the second molding layer, wherein the second conductive coil is interweaved with the second portion of the first conductive coil in the second molding layer;
at least one first via extending across at least a portion of the first dielectric layer from the second molding layer toward the first molding layer;
at least one conductive line disposed in the first dielectric layer and electrically coupled to the at least one first via, wherein the at least one first via and the at least one conductive line electrically couple the first portion with the second portion such that the first and second portions are laterally offset from one another;
a second dielectric layer disposed between the first dielectric layer and the first molding layer;
at least one second via disposed in the second dielectric layer and electrically coupling the at least one conductive line with the first portion of the first conductive coil, wherein the at least one conductive line is laterally disposed between the at least one first via and the at least one second via; and
an integrated circuit die formed in the second molding layer and electrically coupled to the second conductive coil.

20. The device of claim 1 , wherein:
the first portion of the first conductive coil includes a plurality of third vias extending through the first molding layer,
the second portion of the first conductive coil includes a plurality of fourth vias extending through the second moldi

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liang Shih-Wei
• Kuo Hung-Yi
• Tsai Hao-Yi
• Tseng Ming-Hung
• Tu Hsien-Ming

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title