Method for fabricating semiconductor package and semiconductor package using the same

Patent metadata

Field	Value
Publication number	US-11569163-B2
Application number	US-202117498099-A
Country	US
Kind code	B2
Filing date	Oct 11, 2021
Priority date	Dec 8, 2015
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer.

First claim

The invention claimed is:

1. A method of manufacturing an electronic device, the method comprising:
forming a first conductive pattern (CP 1 ) on a carrier, the first conductive pattern (CP 1 ) comprising a first CP 1 side facing a first direction, a second CP 1 side opposite the first CP side, and a lateral CP 1 side between the first CP 1 side and the second CP 1 side;
after said forming the first conductive pattern (CP 1 ), forming a molded encapsulant (ME) comprising a first ME side, and a second ME side opposite the first ME side; and
forming a conductive via;
wherein:
the conductive via is coupled to the first CP 1 side; and
the molded encapsulant (ME) laterally surrounds the first conductive pattern (CP 1 ) and the conductive via.

2. The method of claim 1 , where the molded encapsulant (ME) laterally surrounds an entirety of the first conductive pattern (CP 1 ) and the conductive via.

3. The method of claim 1 , wherein the first conductive pattern (CP 1 ) and the conductive via combine to form a conductive path that extends completely between the first ME side and the second ME side.

4. The method of claim 1 , wherein the second ME side is coplanar with the second CP 1 side.

5. The method of claim 1 , wherein the first ME side is coplanar with a first surface of the conductive via.

6. The method of claim 1 , comprising after said forming the first conductive pattern (CP 1 ), after said forming the molded encapsulant (ME), and after said forming the conductive via, plating a metal on the conductive via.

7. The method of claim 1 , comprising forming a second conductive pattern (CP 2 ) directly on the conductive via and directly on the molded encapsulant (ME), where the second conductive pattern (CP 2 ) comprises a first CP 2 side facing the first direction, a second CP 2 side opposite the first CP 2 side, and a lateral CP 2 side between the first CP 2 side and the second CP 2 side.

8. The method of claim 1 , wherein said forming the molded encapsulant (ME) is performed prior to said forming the second conductive pattern (CP 2 ).

9. A method of manufacturing an electronic device, the method comprising:
forming a first conductive pattern (CP 1 ) comprising a first CP 1 side facing a first direction, a second CP 1 side opposite the first CP side, and a lateral CP 1 side between the first CP 1 side and the second CP 1 side;
forming a molded encapsulant (ME) comprising a first ME side facing the first direction, and a second ME side opposite the first ME side;
forming a conductive via; and
after said forming the first conductive pattern (CP 1 ), after said forming the molded encapsulant (ME), and after said forming the conductive via, forming a second conductive pattern (CP 2 ) on the conductive via and on the first ME side, the second conductive pattern (CP 2 ) comprising a first CP 2 side facing the first direction, a second CP 2 side opposite the first CP 2 side, and a lateral CP 2 side between the first CP 2 side and the second CP 2 side,
wherein:
the conductive via is coupled to the first CP 1 side;
the conductive via is coupled to the second CP 2 side; and
the molded encapsulant (ME) laterally surrounds the first conductive pattern (CP 1 ) and the conductive via.

10. The method of claim 9 , comprising forming a solder mask on the second conductive pattern (CP 2 ) and on the molded encapsulant (ME).

11. The method of claim 10 , wherein the solder mask is thicker than the second conductive layer.

12. The method of claim 10 , wherein the solder mask comprises a lateral side that is coplaner with the lateral ME side.

13. The method of claim 10 , wherein the solder mask comprises an aperture, and the method comprises forming a conductive bump that extends through the aperture and is coupled to the first CP 2 side.

14. The method of claim 9 , wherein the second conductive pattern (CP 2 ) directly contacts the first ME side.

15. An electronic device comprising:
a first conductive pattern (CP 1 ) comprising a first CP 1 side facing a first direction, a second CP 1 side opposite the first CP side, and a lateral CP 1 side between the first CP 1 side and the second CP 1 side;
a molded encapsulant (ME) comprising a first ME side facing the first direction, and a second ME side opposite the first ME side; and
a conductive via;
wherein:
the conductive via is coupled to the first CP 1 side; and
the molded encapsulant (ME) laterally surrounds the first conductive pattern (CP 1 ) and the conductive via.

16. The electronic device of claim 15 , comprising a second conductive pattern (CP 2 ) on the conductive via and on the first ME side, the second conductive pattern (CP 2 ) comprising a first CP 2 side facing the first direction, a second CP 2 side opposite the first CP 2 side and coupled to the conductive via, and a lateral CP 2 side between the first CP 2 side and the second CP 2 side.

17. The electronic device of claim 16 , wherein the molded encapsulant (ME) laterally surrounds an entirety of the second conductive pattern (CP 2 ).

18. The electronic device of claim 16 , comprising a solder mask on the second conductive pattern (CP 2 ) and on the first ME side.

19. The electronic device of claim 18 , wherein the solder mask comprises an aperture, and the method comprises forming a conductive bump that extends through the aperture and is coupled to the first CP 2 side.

20. The electronic device of claim 18 , wherein the solder mask comprises a lateral side that is coplaner with the lateral ME side.

Assignees

• Amkor Tech Singapore Holding Pte Ltd

Inventors

• Lee Seung Woo
• Kim Byong Jin
• Bang Won Bae
• Kang Sang Goo

Classifications

• H01L2924/15311

  Electricity · mapped topic

• H01L2224/16225

  Electricity · mapped topic

• H01L23/49822

  Electricity · mapped topic

• H01L23/3114

  Electricity · mapped topic

• H01L23/49827

  Electricity · mapped topic