Method for fabricating semiconductor package and semiconductor package using the same

Patent metadata

Field	Value
Publication number	US-11145588-B2
Application number	US-201916673032-A
Country	US
Kind code	B2
Filing date	Nov 4, 2019
Priority date	Dec 8, 2015
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer.

First claim

The invention claimed is:

1. An electronic device comprising:
a substrate comprising:
a first molded encapsulant having an upper encapsulant side and a lower encapsulant side;
a first conductive pattern at the upper encapsulant side and embedded in the upper encapsulant side of the first molded encapsulant;
a second conductive pattern at the lower encapsulant side, where an upper side of the second conductive pattern is vertically lower than a lower side of the first conductive pattern; and
a conductive path that extends through the first molded encapsulant and electrically connects the first conductive pattern to the second conductive pattern;

an electronic component mounted on the substrate and electrically connected to the first and second conductive patterns; and
a second molded encapsulant over the first molded encapsulant and at least laterally surrounding the electronic component.

2. The electronic device of claim 1 , wherein the second conductive pattern comprises a plated metal pattern comprising a flat lower side.

3. The electronic device of claim 1 , comprising an under bump metallization on a lower side of the second conductive pattern.

4. The electronic device of claim 1 , wherein the conductive path extends vertically through the first molded encapsulant and comprises sloped sidewalls.

5. The electronic device of claim 1 , wherein the electronic component comprises an active side and a passive side, the active side facing the substrate.

6. The electronic device of claim 1 , wherein:
the electronic component is mounted on an upper side of the substrate; and
the electronic component comprises a contact that is soldered to the first conductive pattern.

7. The electronic device of claim 1 , comprising a vertical gap between the first and second conductive patterns.

8. The electronic device of claim 7 , wherein a portion of the first molded encapsulant is directly vertically between the first and second conductive patterns.

9. An electronic device comprising:
a substrate comprising:
a first molded encapsulant having an upper encapsulant side and a lower encapsulant side;
a first conductive pattern at the upper encapsulant side and embedded in the upper encapsulant side;
a second conductive pattern at the lower encapsulant side; and
a conductive path that extends through the first molded encapsulant and electrically connects the first conductive pattern to the second conductive pattern;

an electronic component mounted on an upper side of the substrate and electrically connected to the first and second conductive patterns;
a conductive bump mounted on a lower side of the substrate; and
a second molded encapsulant over the first molded encapsulant and at least laterally surrounding the electronic component.

10. The electronic device of claim 9 , comprising an under bump metallization on the second conductive pattern and positioned directly vertically between the conductive bump and the second conductive pattern.

11. The electronic device of claim 9 , wherein the conductive bump comprises a solder ball.

12. The electronic device of claim 9 , wherein the conductive bump is positioned directly vertically below the electronic component.

13. The electronic device of claim 9 , wherein the first conductive pattern and the second conductive pattern each have a respective top and bottom horizontal side.

14. The electronic device of claim 13 , wherein the conductive path extends vertically between the bottom horizontal side of the first conductive pattern and the top horizontal side of the second conductive pattern.

15. The electronic device of claim 9 , wherein a portion of the first molded encapsulant is directly vertically between the first and second conductive patterns.

16. A method of manufacturing an electronic device, the method comprising:
providing a substrate comprising:
a first molded encapsulant having an upper encapsulant side and a lower encapsulant side;
a first conductive pattern at the upper encapsulant side and embedded in the upper encapsulant side;
a second conductive pattern at the lower encapsulant side; and
a conductive path that extends through the first molded encapsulant and electrically connects the first conductive pattern to the second conductive pattern;

mounting an electronic component on the substrate and electrically connected to the first and second conductive patterns; and
forming a second molded encapsulant over the first molded encapsulant and at least laterally surrounding the electronic component.

17. The method of claim 16 , wherein an upper side of the second conductive pattern is vertically lower than a lower side of the first conductive pattern.

18. The method of claim 17 , wherein a portion of the first molded encapsulant is directly vertically between the upper side of the second conductive pattern and the lower side of the first conductive pattern.

19. The method of claim 16 , wherein said mounting the electronic component comprises mounting the electronic component on an upper side of the substrate, and further comprising forming a conductive bump on a lower side of the substrate.

20. The method of claim 19 , further comprising forming an under bump metallization on the second conductive pattern and positioned directly vertically between the conductive bump and the second conductive pattern.

Assignees

• Amkor Tech Singapore Holding Pte Ltd

Inventors

• Lee Seung Woo
• Kim Byong Jin
• Bang Won Bae
• Kang Sang Goo

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W74/131

  the semiconductor body being only partially enclosed · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title