Method of contact patterning of thin film transistors for embedded DRAM using a multi-layer hardmask

Patent metadata

Field	Value
Publication number	US-11563107-B2
Application number	US-201916361881-A
Country	US
Kind code	B2
Filing date	Mar 22, 2019
Priority date	Mar 22, 2019
Publication date	Jan 24, 2023
Grant date	Jan 24, 2023

Abstract

An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
one or more backend-of-line (BEOL) interconnects formed over a first ILD layer;
an etch stop layer over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects;
an array of BEOL thin-film-transistors (TFTs) over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions, and wherein each of the TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, each of the BEOL TFTs comprising a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein; and
contacts formed over the source and drain regions of each of BEOL TFTs.

2. The integrated circuit structure of claim 1 , wherein the oxide-based semiconductor channel layer comprises one of: tin oxide, antimony oxide, indium oxide, indium tin oxide, indium gallium zinc oxide (IGZO), titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide or tungsten oxide.

3. The integrated circuit structure of claim 1 , wherein a pitch of the BEOL TFTs in a parallel-to-gate direction is approximately 120-150 nm.

4. The integrated circuit structure of claim 1 , wherein a pitch of the BEOL TFTs in an orthogonal-to-gate direction is approximately 93-123 nm.

5. The integrated circuit structure of claim 1 , wherein individual ones of the BEOL TFTs are approximately 95-125 nm in size in a parallel-to-gate direction.

6. The integrated circuit structure of claim 1 , wherein individual ones of the BEOL TFTs are approximately 58-88 nm in size in an orthogonal-to-gate direction.

7. The integrated circuit structure of claim 1 , wherein the BEOL TFTs are spaced apart in a parallel-to-gate direction by approximately 25 nm, and are spaced apart in an orthogonal-to-gate direction by approximately 35 nm.

8. The integrated circuit structure of claim 1 , wherein the integrated circuit structure comprises an embedded dynamic random access memory (eDRAM).

9. A method of fabricating a memory device, the method comprising:
forming one or more backend-of-line (BEOL) interconnects over a first ILD layer;
forming an etch stop layer over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects;
forming an array of BEOL thin-film-transistors (TFTs) over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions, and wherein each of the TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, each of the BEOL TFTs comprising a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein; and
forming contacts over the source and drain regions of each of BEOL TFTs.

10. The method of claim 9 , wherein the oxide-based semiconductor channel layer comprises one of: tin oxide, antimony oxide, indium oxide, indium tin oxide, indium gallium zinc oxide (IGZO), titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide or tungsten oxide.

11. The method of claim 9 , wherein a pitch of the BEOL TFTs in a parallel-to-gate direction is approximately 120-150 nm.

12. The method of claim 9 , wherein a pitch of the BEOL TFTs in an orthogonal-to-gate direction is approximately 93-123 nm.

13. The method of claim 9 , wherein individual ones of the BEOL TFTs are approximately 95-125 nm in size in a parallel-to-gate direction.

14. The method of claim 9 , wherein individual ones of the BEOL TFTs are approximately 58-88 nm in size in an orthogonal-to-gate direction.

15. The method of claim 9 , wherein the BEOL TFTs are spaced apart in a parallel-to-gate direction by approximately 25 nm, and are spaced apart in an orthogonal-to-gate direction by approximately 35 nm.

16. The method of claim 9 , wherein the integrated circuit structure comprises an embedded dynamic random access memory (eDRAM).

17. A method of fabricating a memory device, the method comprising:
forming an array of backend-of-line (BEOL) thin film transistors (TFTs), the BEOL TFTs having an oxide channel;
forming a multilayer hardmask for contact patterning of the BEOL TFTs, where the multilayer hardmask comprises a metal hardmask and a dielectric hardmask having different etch selectivities;
performing a litho-etch-litho-etch patterning to enable two different etch bias tunings including, a first etch bias tuning for patterning the dielectric hardmask in an orthogonal-to-gate direction (OGD), and a second etch bias tuning for patterning the metal hardmask in a parallel-to-gate direction (PGD) to define contact hole locations;
performing a contact open dry etch process to remove the dielectric hardmask entirely, and to remove material in the contact hole locations down to the oxide channel to create contact holes;
performing a wet clean process to remove the metal hardmask entirely, wherein the wet clean is compatible with the oxide channel, such that the wet clean does not remove or damage the oxide channel; and
performing a metal fill and polish over the contact holes to create contacts.

18. The method of claim 17 further comprising:
patterning the metal hardmask to a thickness of approximately 10-35 nm, and patterning the dielectric hardmask to a thickness of approximately 10-30 nm.

19. The method of claim 17 further comprising:
patterning the metal hardmask and the dielectric hardmask such that a number of material layers comprising the metal hardmask is different than a number of material layers comprising the dielectric hardmask.

20. The method of claim 17 wherein performing the litho-etch-litho-etch patterning further comprises:
performing a first lithographic etch process to define a first pattern in the OGD to transfer to the dielectric hardmask; and
performing a first contact dry etch process having a chemistry selective to the metal hardmask and non-selective to the dielectric hardmask to remove the dielectric hardmask over the contact hole locations in the OGD.

21. The method of claim 20 wherein performing the litho-etch-litho-etch patterning further comprises:
performing a second lithographic etch process to define a second pattern in the PGD to transfer to the metal hardmask; and
performing a second contact dry etch process having a chemistry selective to the dielectric hardmask and non-selective to the metal hardmask to remove the metal hardmask over the contact hole locations in the PGD.

22. The method of claim 17 , wherein the oxide-based semiconductor channel layer comprises one of: tin oxide, antimony oxide, indium oxide, indium tin oxide, indium gallium zinc oxide (IGZO), titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide or tungsten oxide.

23. The method of claim 17 , wherein a pitch of the BEOL TFTs in a parallel-to-gate direction is approximately 120-150 nm.

24. The method of claim 17 , wherein a pitch of the BEOL TFTs in an orthogonal-to-gate direction is approximately 93-123 nm.

25. The method of claim 17 , wh

Assignees

• Intel Corp

Inventors

• Ku Chieh-Jen
• Sell Bernhard
• Wang Pei-Hua
• Mehta Nikhil
• Zhou Shu
• Stoeger Jared
• Gardiner Allen B
• Garg Akash
• Ogadhoh Shem
• Hadagali Vinaykumar
• Lajoie Travis W

Classifications

• H01L29/78696

  Electricity · mapped topic

• H01L27/10873

  Electricity · mapped topic

• H01L29/66742 Primary

  Electricity · mapped topic

• H01L27/10805

  Electricity · mapped topic

• H10P95/066

  the removal being a selective chemical etching step, e.g. selective dry etching through a mask · CPC title