Method of contact patterning of thin film transistors for embedded DRAM using a multi-layer hardmask
US-11563107-B2 · Jan 24, 2023 · US
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Patent family 69701124
This patent family groups 2 related publications across US. Members often share priority claims or equivalent filings in different countries.
| Field | Value |
|---|---|
| Family ID | 69701124 |
| Family type | — |
| Earliest priority | Mar 22, 2019 |
| First filing country | US |
| Member publications | 2 |
| Countries | US |
| Representative publication | US11563107B2 — Method of contact patterning of thin film transistors for embedded DRAM using a multi-layer hardmask |
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US11563107B2 — Method of contact patterning of thin film transistors for embedded DRAM using a multi-layer hardmask (published Jan 24, 2023)
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