Punch-through interconnect feature to couple upper electrodes of capacitors of multi-level memory arrays
US-12476183-B2 · Nov 18, 2025 · US
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Stoeger Jared patents
Stoeger Jared is listed as an inventor on 8 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Stoeger Jared |
| Total patents | 8 |
| First publication | Sep 24, 2020 |
| Latest publication | Nov 18, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Capacitor connections in dielectric layers
US-12426247-B2 · Sep 23, 2025 · US
Capacitor connections in dielectric layers
US-2024049450-A1 · Feb 8, 2024 · US
Capacitor connections in dielectric layers
US-11832438-B2 · Nov 28, 2023 · US
Punch-through interconnect feature to couple upper electrodes of capacitors of multi-level memory arrays
US-2023290722-A1 · Sep 14, 2023 · US
Method of contact patterning of thin film transistors for embedded DRAM using a multi-layer hardmask
US-11563107-B2 · Jan 24, 2023 · US
Capacitor connections in dielectric layers
US-2020411525-A1 · Dec 31, 2020 · US
Method of contact patterning of thin film transistors for embedded dram using a multi-layer hardmask
US-2020303520-A1 · Sep 24, 2020 · US
Recent patents
Latest publications not already listed above.
No data yet.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 8 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10B12/315 | 8 |
| H10B12/0335 | 6 |
| H10D86/441 | 6 |
| H10D86/423 | 6 |
| H10D86/411 | 6 |