Voltage adjust circuit and operation method thereof

Patent metadata

Field	Value
Publication number	US-11558043-B2
Application number	US-202117516730-A
Country	US
Kind code	B2
Filing date	Nov 2, 2021
Priority date	May 12, 2021
Publication date	Jan 17, 2023
Grant date	Jan 17, 2023

Abstract

The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.

First claim

What is claimed is:

1. A voltage adjust circuit, comprising:
a buffer circuit, comprising a plurality of pull-up transistors and a plurality of pull-down transistors, wherein the pull-up transistors are electrically coupled between an output terminal of the voltage adjust circuit and a system high voltage terminal, wherein the pull-down transistors are electrically coupled between the output terminal of the voltage adjust circuit and a system low voltage terminal, wherein the pull-up transistors comprises two adjacent pull-up transistors, wherein the pull-down transistors comprises two adjacent pull-down transistors;
a level shifter, configured to generate a plurality of control signals according to a input signal;
a bias circuit, electrically coupled between the level shifter and the buffer circuit, wherein the bias circuit is configured to successively enable the pull-up transistors or the pull-down transistors according to the control signals, such that a voltage level of the output terminal is switched between a voltage level of the system high voltage terminal and a voltage level of the system low voltage terminal; and
a cross-voltage-suppression circuit, electrically coupled to the pull-up transistors and the pull-down transistors, wherein the cross-voltage-suppression circuit is configured to suppress transient and static voltage stress between two terminals of the pull-up transistors or the pull-down transistors in response to switching the voltage level of the output terminal between the voltage level of the system high voltage terminal and the voltage level of the system low voltage terminal, wherein the cross-voltage-suppression circuit comprises:
a pull-up-suppression transistor, with a drain terminal and a source terminal respectively coupled to a source terminal and a gate terminal of one of the two adjacent pull-up transistors, with a gate terminal coupled to a gate terminal of the other one of the two adjacent pull-up transistors; and
a pull-down-suppression transistor, with a drain terminal and a source terminal respectively coupled to a source terminal and a gate terminal of one of the two adjacent pull-down transistors, with a gate terminal coupled to a gate terminal of the other one of the two adjacent pull-down transistors.

2. The voltage adjust circuit of claim 1 , wherein,
the pull-up-suppression transistor with the drain terminal coupled to the source terminal of the one of the two adjacent pull-up transistors, with the source terminal coupled to the gate terminal of the one of the two adjacent pull-up transistors; and
the pull-down suppression transistor, with the drain terminal coupled to the source terminal of the one of the two adjacent pull-down transistors, with the source terminal coupled to the gate terminal of the one of the two adjacent pull-down transistors.

3. The voltage adjust circuit of claim 2 , wherein the voltage level of the system low voltage terminal has a negative value.

4. The voltage adjust circuit of claim 2 , wherein the bias circuit further comprises:
a plurality of voltage divider transistors, electrically coupled between the system high voltage terminal and the system low voltage terminal, wherein the voltage divider transistors are configured to provide a first static bias voltage to a first node and provide a second static bias voltage to a second node; and
an inner bias circuit, electrically between the first node and the second node, wherein the inner bias circuit is configured to provide a plurality of inner bias voltages to the buffer circuit.

5. The voltage adjust circuit of claim 4 , wherein the bias circuit further comprises a plurality of switches, the switches electrically between the system high voltage terminal and the system low voltage terminal, wherein the level shifter provides the control signals to the switches according to the input signal, such that the switches provide a plurality of dynamic bias voltages to the buffer circuit and the inner bias circuit according to the control signals.

6. The voltage adjust circuit of claim 5 , wherein the switches comprises:
a first switch, electrically coupled between the system high voltage terminal and the first node, wherein the first switch is configured to provide a first dynamic bias voltage of the dynamic bias voltages to a gate terminal of one of the pull-up transistors closest to the system high voltage terminal according to one of the control signals; and
a second switch, electrically coupled between the second node and the system low voltage terminal, wherein the second switch is configured to provide a second dynamic bias voltage of the dynamic bias voltages to the a gate terminal of one of the pull-down transistors closest to the system low voltage terminal according to another of the control signals; and
a third switch, electrically coupled between the first switch and the second switch, wherein the third switch is configured to provide a third dynamic bias voltage of the dynamic bias voltages to the inner bias circuit according to the other of the control signals.

7. The voltage adjust circuit of claim 6 , wherein the pull-up transistors and the pull-down transistors of the buffer circuit are respectively enabled according to the first dynamic bias voltage, the first static bias voltage, the second dynamic bias voltage, the second static bias voltage and the inner bias voltages.

8. The voltage adjust circuit of claim 7 , wherein,
when the input signal has a first logic level, the pull-up transistors are turned off according to the first dynamic bias voltage, the first static bias voltage and a part of the inner bias voltages, and the pull-down transistors are turned on according to the second dynamic bias voltage, the second static bias voltage and the other part of the inner bias voltages.

9. The voltage adjust circuit of claim 7 , wherein,
when the input signal has a second logic level, the pull-up transistors are turned on according to the first dynamic bias voltage, the first static bias voltage and a part of the inner bias voltages, and the pull-down transistors are turned off according to the second dynamic bias voltage, the second static bias voltage and the other part of the inner bias voltages.

10. The voltage adjust circuit of claim 7 , wherein the pull-up transistors comprises two pull-up transistors closest to the output terminal, wherein the pull-down transistors comprises two pull-down transistors closest to the output terminal, wherein the bias circuit is further comprises:
a first capacitor, electrically coupled between gate terminals of the two pull-up transistors closest to the output terminal; and
a second capacitor, electrically coupled between gate terminals of the two pull-down transistors closest to the output terminal.

11. The voltage adjust circuit of claim 7 , wherein the pull-down transistors are implemented by N-type metal oxide semiconductor with deep N well, wherein deep N well of each pull-down transistors is electrically coupled to the system high voltage terminal, wherein base terminal and source terminal of each pull-down transistors are electrically coupled to each other.

12. A method, for operating a voltage adjust circuit comprising a buffer circuit and a pull-up suppression transistor, wherein the buffer circuit comprises a plurality of pull-up transistors electrically coupled in series between a system high voltage terminal and an output terminal of the voltage adjust circuit and a plurality of pull-down transistors electrically coupled in series between the output terminal of the voltage adjust circuit and a system low voltage terminal, wherein the pull-up transistors comprises two adjacent pull-up transi

Assignees

• Au Optronics Corp

Inventors

• Lu Yi-Chen
• Li Hsu-Chi
• Chen Yi-Jan
• Jaw Boy-Yiing
• Chuang Chin-Tang
• Chen Chung-Hung

Classifications

• G05F1/561 Primary

  Voltage to current converters (amplifiers H03F) · CPC title

• H03K19/017509

  Interface arrangements · CPC title

• H03K5/02 Primary

  by amplifying (H03K5/04 takes precedence) · CPC title

• H03K5/023

  using field effect transistors · CPC title