Input/output circuit

Patent metadata

Field	Value
Publication number	US-10686434-B2
Application number	US-201816206577-A
Country	US
Kind code	B2
Filing date	Nov 30, 2018
Priority date	Feb 25, 2015
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power node and the output node, and a contending transistor coupled between the node and a second power node configured to carry a second voltage having a second voltage level. The circuit generates a signal at the output node that ranges between the first voltage level and a third voltage level, the contending transistor couples the node with the second power node responsive to the signal, a difference between the first voltage level and the second voltage level has a first magnitude, a difference between the first voltage level and the third voltage level has a second magnitude, and the second magnitude is a multiple of the first magnitude having a value greater than one.

First claim

What is claimed is:

1. A circuit comprising:
a first power node configured to carry a first voltage having a first voltage level;
an output node;
first and second cascode transistors coupled between the first power node and the output node and to each other at a node;
a bias circuit configured to use the first and second cascode transistors to generate a signal at the output node that ranges between the first voltage level and a third voltage level;
a control circuit configured to generate a first control signal based on the signal; and
a contending transistor configured to, responsive to the first control signal, couple the node to a second power node configured to carry a second voltage having a second voltage level,
wherein
a difference between the first voltage level and the second voltage level has a first magnitude,
a difference between the first voltage level and the third voltage level has a second magnitude, and
the second magnitude is a multiple of the first magnitude having a value greater than one.

2. The circuit of claim 1 , further comprising an input node configured to receive an input signal having a voltage range corresponding to the first magnitude, wherein the circuit is configured to generate the signal at the output node responsive to the input signal.

3. The circuit of claim 2 , wherein
the bias circuit is configured to:
generate a second control signal based on the input signal, and
couple the node with the first power node responsive to the second control signal,

the control circuit comprises an adjustable delay circuit configured to generate a delayed signal based on the second control signal, and
the control circuit is configured to generate the first control signal responsive to the delayed signal.

4. The circuit of claim 3 , wherein
the adjustable delay circuit is configured to generate the delayed signal by applying a delay to the second control signal, and
the delay is a function of a capacitive load at the output node.

5. The circuit of claim 4 , wherein the delay depends on a driving capability of the first cascode transistor configured to couple the node with the first power node.

6. The circuit of claim 3 , wherein the adjustable delay circuit is configured to operate in a power domain defined by the first power node and the second power node.

7. The circuit of claim 3 , wherein the control circuit further comprises a logic gate configured to generate the first control signal based on the second control signal and the delayed signal, wherein the contending transistor is configured to receive the first control signal.

8. The circuit of claim 1 , wherein
the first cascode transistor is coupled between the node and the first power node,
the contending transistor is one type of an N-type transistor or a P-type transistor, and
the first cascode transistor is the other type of the N-type transistor or the P-type transistor.

9. The circuit of claim 8 , wherein the contending transistor has a driving capability equal to or less than a driving capability of the first cascode transistor.

10. A method comprising:
using a bias circuit to control first and second cascode transistors coupled between a first power node and an output node of a circuit, thereby generating a signal at the output node, the signal ranging between a first voltage level carried on the first power node and a second voltage level;
responsive to the signal, generating a control signal using a control circuit; and
responsive to the control signal, using a contending transistor to electrically couple a node between the first and second cascode transistors to a second power node carrying a third voltage level,
wherein,
a difference between the first voltage level and the second voltage level has a first magnitude,
a difference between the first voltage level and the third voltage level has a second magnitude, and
the first magnitude is a multiple of the second magnitude having a value greater than one.

11. The method of claim 10 , further comprising, responsive to the control signal, using the contending transistor to electrically decouple the node from the second power node following a delay period.

12. The method of claim 11 , wherein the using the contending transistor to electrically decouple the node from the second power node comprises controlling the delay period based on a capacitive load at the output node.

13. The method of claim 10 , wherein the generating the signal comprises using the first cascode transistor to electrically couple the node with the first power node while the node is electrically coupled with the second power node.

14. The method of claim 10 , further comprising using the contending transistor to electrically couple the node with the second power node while using the first cascode transistor to electrically decouple the node from the first power node.

15. The method of claim 10 , further comprising using the contending transistor to electrically couple the node with the second power node after using the first cascode transistor to electrically decouple the node from the first power node.

16. A circuit comprising:
a first power node configured to carry a first voltage having a first voltage level;
a second power node configured to carry a second voltage having a second voltage level;
an output node;
first and second cascode transistors coupled between the first power node and the output node and to each other at a first node;
third and fourth cascode transistors coupled between the output node and the second power node and to each other at a second node;
a bias circuit configured to use the first through fourth cascode transistors to generate a signal at the output node that ranges between the first voltage level and the second voltage level;
first and second control circuits configured to generate respective first and second control signals based on the signal;
a first contending transistor configured to, responsive to the first control signal, couple the first node to a third power node configured to carry a third voltage having a third voltage level; and
a second contending transistor configured to, responsive to the second control signal, couple the second node to a fourth power node configured to carry a fourth voltage having a fourth voltage level,
wherein
each of a difference between the first voltage level and the third voltage level and a difference between the second voltage level and the fourth voltage level has a first magnitude,
a difference between the first voltage level and the second voltage level has a second magnitude, and
the second magnitude is a multiple of the first magnitude having a value greater than one.

17. The circuit of claim 16 , wherein the third voltage level is the same as the fourth voltage level.

18. The circuit of claim 16 , wherein
the first voltage level is greater than the second voltage level,
the first contending transistor is an N-type transistor, and
the second contending transistor is a P-type transistor.

19. The circuit of claim 16 , further comprising an input node configured to receive an input signal having a voltage range corresponding to the first magnitude, wherein the circuit is configured to, responsive to the input signal:
for a first delay period, use the first cascode transistor to couple the first node with the first power node while the first node is coupled with the third power node by the first contending transistor, and
for a second delay period, use the third cascode transistor to couple

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chern Chan-Hong
• Huang Tsung-Ching
• Lin Chih-Chang
• Huang Ming-Chieh
• Hsueh Fu-Lung

Classifications

• H03K17/167 Primary

  using parallel switching arrangements · CPC title

• H03K5/1534 Primary

  Transition or edge detectors · CPC title

• H03K19/00315

  in field-effect transistor circuits · CPC title

• H03K5/131

  Digitally controlled · CPC title

• H03K17/6872

  using complementary field-effect transistors · CPC title