Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11557647-B2
Application number	US-201817048174-A
Country	US
Kind code	B2
Filing date	Apr 19, 2018
Priority date	Apr 19, 2018
Publication date	Jan 17, 2023
Grant date	Jan 17, 2023

Abstract

A semiconductor device includes: a drift region of a first conductive type including a contact section and extension sections extending along the main surface of a substrate; column regions of a second conductive type which alternate with the extension sections in a perpendicular direction to the extension direction of the extension sections and each includes an end connecting to the contact section; a well region of a second conductive type which connects to the other end of each column region and tips of the extension sections; and electric field relaxing electrodes which are provided above at least some of residual pn junctions with an insulating film interposed therebetween. Herein, the residual pn junctions are pn junctions other than voltage holding pn junctions formed in interfaces between the extension sections and the column regions.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a substrate;
a drift region of a first conductive type which is provided on a main surface of the substrate, the drift region including a contact section and extension sections extending from part of the contact section along the main surface of the substrate;
column regions of a second conductive type which alternate with the extension sections in a perpendicular direction to the extension direction of the extension sections of the drift region and at least some of the column regions include an end connecting to the contact section;
a well region of a second conductive type which connects to the other end of each column region and tips of the extension sections of the drift region;
a first main electrode which electrically connects to the well region;
a second main electrode which electrically connects to the contact section of the drift region;
an insulating film which is provided above the drift region, the column regions, and the well region; and
electric field relaxing electrodes which are provided above at least some peripheral pn junctions with the insulating film interposed therebetween, the peripheral pn junctions being pn junctions other than voltage holding pn junctions formed in interfaces between the extension sections of the drift region and the column regions,
wherein the electric field relaxing electrodes are provided above at least some of the peripheral pn junctions that are adjacent to the first main electrode and each include a section electrically connecting to the first main electrode,
the electric field relaxing electrodes are provided above at least any of the peripheral pn junctions where the extension sections of the drift region connect to the well region and the peripheral pn junctions where the contact section of the drift region connects to the column regions,
wherein the peripheral pn junctions in which the electric field relaxing electrodes are arranged above include only first peripheral pn junctions where the well region connects to the tips of the extension sections and second peripheral pn junctions, wherein ends of the column regions connect to the contact section.

2. The semiconductor device according to claim 1 ,
wherein
the electric field relaxing electrodes are provided above at least some of the peripheral pn junctions that are adjacent to the second main electrode and each include a section electrically connecting to the second main electrode.

3. The semiconductor device according to claim 1 ,
wherein
width of each of the electric field relaxing electrodes in the perpendicular direction to the extension direction is greater in a region above any peripheral pn junction than in other regions being regions excluding the region above the peripheral pn junction.

4. The semiconductor device according to claim 1 ,
wherein the substrate is an insulating substrate.

5. The semiconductor device according to claim 1 , wherein a distance between a lower surface of each of the electric field relaxing electrodes and the substrate decreases gradually so that the distance from the peripheral pn junction below the electric field relaxing electrode to each section of the lower surface of the electric field relaxing electrode which faces the substrate is substantially constant.

6. The semiconductor device according to claim 1 , wherein the drift region further includes a layered section which is layered on the column regions in the thickness direction of the substrate with an end connecting to the contact section and the other end connecting to the well region.

7. The semiconductor device according to claim 1 , wherein the semiconductor device has a structure in which the extension sections of the drift region and the column regions are stacked on top of each other in the thickness direction of the substrate.

8. The semiconductor device according to claim 1 , wherein impurity concentrations of the extension sections and the column regions are set so that in an off state where main current flowing between the first and second main electrodes is shut off, the extension sections of the drift region and the column regions are depleted due to depletion layers spreading from the voltage holding pn junctions.

9. The semiconductor device according to claim 1 , wherein
the tips of the extension sections of the drift region and the first main electrode are electrically connected through interfaces having an energy barrier,
the second main electrode forms an ohmic contact with the contact section of the drift region, and
the semiconductor device operates as a Schottky barrier diode with the first main electrode as an anode electrode and the second main electrode as a cathode electrode.

10. The semiconductor device according to claim 1 , further comprising a control electrode provided in a current path of a main current flowing between the first and second main electrodes, wherein
the first main electrode forms an ohmic contact with the well region,
the second main electrode forms an ohmic contact with the contact section of the drift region, and
the semiconductor device operates as a transistor in which the control electrode controls the main current.

11. A method of manufacturing a semiconductor device, comprising:
forming a drift region of a first conductive type on a main surface of a substrate, the drift region including
a contact section and extension sections extending from part of the contact section along a main surface of the substrate;
forming column regions of a second conductive type which alternate with the extension sections in a perpendicular direction to the extension direction of the extension sections of the drift region and at least some of the column regions include an end connecting to the contact section of the drift region;
forming a well region of a second conductive type which connects to the other end of each column region and tips of the extension sections of the drift region;
forming a first main electrode which electrically connects to the well region;
forming a second main electrode which electrically connects to the contact section of the drift region;
forming an insulating film which is provided above the drift region, the column regions, and the well region; and
forming electric field relaxing electrodes which are provided above at least some of peripheral pn junctions with the insulating film interposed therebetween, the peripheral pn junctions being pn junctions other than voltage holding pn junctions formed in interfaces between the extension sections of the drift region and the column regions, wherein
the electric field relaxing electrodes are provided above at least some of the peripheral pn junctions that are adjacent to the first main electrode and each include a section electrically connecting to the first main electrode,
the electric field relaxing electrodes are provided above at least any of the peripheral pn junctions where the extension sections of the drift region connect to the well region and the peripheral pn junctions where the contact section of the drift region connects to the column regions,
wherein the peripheral pn junctions in which the electric field relaxing electrodes are arranged above include only first peripheral pn junctions where the well region connects to the tips of the extension sections and a second peripheral pn junctions.

12. The method of manufacturing a semiconductor device according to claim 11 , wherein the drift region and the column regions are formed by ion implantation of impurities into the substrate.

Assignees

• Nissan Motor

Inventors

• Marui Toshiharu
• Hayashi Tetsuya
• Numakura Keiichiro
• Ni Wei
• Tanaka Ryota
• Takemoto Keisuke

Classifications

• H01L29/1058

  Electricity · mapped topic

• H01L29/45

  Electricity · mapped topic

• H01L29/0634 Primary

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title