Semiconductor device and semiconductor device fabrication method

Patent metadata

Field	Value
Publication number	US-9653595-B2
Application number	US-201414482742-A
Country	US
Kind code	B2
Filing date	Sep 10, 2014
Priority date	Jul 19, 2012
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

An n − drift layer is a parallel pn layer having an n-type region and a p-type region are alternately arranged in the direction parallel to the main surface so as to come into contact with each other, and have a width in a direction parallel to the main surface of the substrate which is less than a length in a direction perpendicular to the main surface of the substrate. A second-main-surface-side lower end portion of the p-type region has a structure in which a high-concentration lower end portion and a low-concentration lower end portion of a p-type low-concentration region are repeated at a predetermined pitch in the direction parallel to the main surface of the substrate. It is possible to provide a super junction MOS semiconductor device which can improve a trade-off relationship between turn-off loss and turn-off dv/dt and improve avalanche resistance.

First claim

What is claimed is:

1. A semiconductor device comprising:
an insulated gate structure that is provided on a first main surface of a first-conductivity-type semiconductor substrate; and
a drift layer that is provided between the first main surface of the first-conductivity-type semiconductor substrate and a second main surface opposite to the first main surface,
wherein the drift layer is a parallel pn layer including a first-conductivity-type region in which a width in a direction parallel to the first main surface is less than a length in a direction perpendicular to the first main surface and a second-conductivity-type region in which a width in the direction parallel to the first main surface is less than a length in the direction perpendicular to the first main surface, wherein a planar pattern of the drift layer under the insulated gate structure is a stripe pattern,
the first-conductivity-type region and the second-conductivity-type region are alternately arranged in the direction parallel to the first main surface so as to come into contact with each other,
a pn junction between the first-conductivity-type region and the second-conductivity-type region extends in the direction perpendicular to the first main surface, and
a second-conductivity-type second-main-surface-side region having an impurity concentration distribution in which high impurity concentration and low impurity concentration are repeated at a predetermined pitch in the direction parallel to the first main surface, the second-conductivity-type second-main-surface-side region contacting an end of the second-conductivity-type region that is closest to the second main surface,
wherein the second-conductivity-type second-main-surface-side region includes: a second-main-surface-side high-concentration region having a higher impurity concentration than the concentration at a bottom of the second-conductivity-type region and a second-main-surface-side low-concentration region having a lower impurity concentration than the concentration at the bottom of the second-conductivity-type region, wherein the second-main-surface-side high-concentration region and the second-main-surface-side low-concentration region are alternately and continuously arranged in a longitudinal direction of the stripe pattern under the insulated gate structure.

2. The semiconductor device according to claim 1 , wherein:
the second-main-surface-side high-concentration region has a larger width than the second-conductivity-type region in the first direction; and
the second-main-surface-side low-concentration region has a smaller width than the second-conductivity-type region in the first direction.

3. The semiconductor device according to claim 1 , wherein the predetermined pitch is less than a pitch between the first-conductivity-type region and the second-conductivity-type region.

4. The semiconductor device according to claim 2 , wherein the predetermined pitch is less than a pitch between the first-conductivity-type region and the second-conductivity-type region.

5. The semiconductor device according to claim 1 , wherein the impurity concentration of the high-concentration region is equal to or greater than 1.2 times the impurity concentration of the low-concentration region and equal to or less than three times the impurity concentration of the low-concentration region.

6. The semiconductor device according to claim 5 , wherein the impurity concentration of the high-concentration region is equal to or less than 2.5 times the impurity concentration of the low-concentration region.

7. A method for fabricating the semiconductor device according to claim 2 , comprising:
a forming step of performing ion implantation using a mask having a stripe-shaped opening portion which extends in the second direction to form the second-main-surface-side region,
wherein the opening portion of the mask has a stripe pattern in which a first opening portion that exposes a portion corresponding to a region for forming the second-main-surface-side high-concentration region and a second opening portion that expose a portion corresponding to a region for forming the second-main-surface-side low-concentration region and has a smaller opening area than the first opening portion are alternately arranged in an extension direction of the stripe.

Assignees

• Fuji Electric Co Ltd

Inventors

• Niimura Yasushi
• Sakata Toshiaki

Classifications

• H10P30/22

  using masks · CPC title

• H10D62/051

  Forming charge compensation regions, e.g. superjunctions · CPC title

• H10D30/66 Primary

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D62/111 Primary

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H01L29/0886

  Electricity · mapped topic