Memory device structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-11545619-B2
Application number	US-202016934341-A
Country	US
Kind code	B2
Filing date	Jul 21, 2020
Priority date	Jul 21, 2020
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.

First claim

What is claimed is:

1. A method for forming a memory device structure, comprising:
providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer, wherein
the substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region, the magnetic tunnel junction cell is over the conductive via, the first etch stop layer covers the first dielectric layer and the magnetic tunnel junction cell, and the first spacer layer is over the first etch stop layer surrounding the magnetic tunnel junction cell and a first upper portion of the first dielectric layer;
removing the first etch stop layer, which is not covered by the first spacer layer; and
removing the first dielectric layer, which is not covered by the first etch stop layer.

2. The method for forming the memory device structure as claimed in claim 1 , further comprising:
providing a second etch stop layer over the substrate, wherein the first dielectric layer is over the second etch stop layer, the conductive via further passes through the second etch stop layer, the second etch stop layer over the second region is exposed after the removing of the first dielectric layer, which is not covered by the first etch stop layer, and the first etch stop layer is thicker than the second etch stop layer.

3. The method for forming the memory device structure as claimed in claim 2 , further comprising:
forming a second dielectric layer over the magnetic tunnel junction cell, the first etch stop layer, the first spacer layer, and the second etch stop layer after removing the first dielectric layer, which is not covered by the first etch stop layer;
removing a portion of the second dielectric layer over the second region to form a trench and a via hole in the second dielectric layer, wherein the trench is over and communicates with the via hole;
forming a conductive layer over the second dielectric layer and in the trench and the via hole; and
removing the conductive layer outside of the trench and the via hole.

4. The method for forming the memory device structure as claimed in claim 3 , wherein the removing of the conductive layer outside of the trench and the via hole further comprises removing a second upper portion of the second dielectric layer and a third upper portion of the magnetic tunnel junction cell.

5. The method for forming the memory device structure as claimed in claim 4 , wherein a first top surface of the magnetic tunnel junction cell, a second top surface of the second dielectric layer, and a third top surface of the conductive layer are substantially coplanar after the removing of the conductive layer outside of the trench and the via hole, the second upper portion of the second dielectric layer, and the third upper portion of the magnetic tunnel junction cell.

6. The method for forming the memory device structure as claimed in claim 5 , wherein the magnetic tunnel junction cell comprises a bottom electrode, a magnetic tunnel junction stack, and a top electrode sequentially stacked over the conductive via, and the top electrode has the first top surface.

7. The method for forming the memory device structure as claimed in claim 1 , further comprising:
providing a second spacer layer between the magnetic tunnel junction cell and the first etch stop layer and between the first upper portion of the first dielectric layer and the first etch stop layer, wherein the removing of the first etch stop layer, which is not covered by the first spacer layer, further comprises removing the first etch stop layer over an upper surface of the second spacer layer.

8. The method for forming the memory device structure as claimed in claim 7 , wherein the first etch stop layer conformally covers the first dielectric layer, the second spacer layer and the magnetic tunnel junction cell before removing the first etch stop layer, which is not covered by the first spacer layer.

9. The method for forming the memory device structure as claimed in claim 1 , wherein a first sidewall of the first etch stop layer and a second sidewall of the first dielectric layer are substantially coplanar after removing the first dielectric layer, which is not covered by the first etch stop layer.

10. The method for forming the memory device structure as claimed in claim 9 , wherein a third sidewall of the first spacer layer and the first sidewall of the first etch stop layer are substantially coplanar after removing the first dielectric layer, which is not covered by the first etch stop layer.

11. A method for forming a memory device structure, comprising:
providing a substrate, a dielectric layer, a conductive via, a bottom electrode, a magnetic tunnel junction stack, a top electrode, an etch stop layer, and a spacer layer, wherein
the substrate has a first region and a second region, the dielectric layer is over the substrate, the conductive via passes through the dielectric layer over the first region, the bottom electrode, the magnetic tunnel junction stack, and the top electrode are sequentially stacked over the conductive via, the spacer layer surrounds the magnetic tunnel junction stack, the bottom electrode, and a first upper portion of the dielectric layer, and the etch stop layer covers a first sidewall of the magnetic tunnel junction stack and is between the magnetic tunnel junction stack and the spacer layer and between the dielectric layer and the spacer layer; and
removing the dielectric layer, which is not covered by the etch stop layer.

12. The method for forming the memory device structure as claimed in claim 11 , wherein the first sidewall of the magnetic tunnel junction stack, a second sidewall of the bottom electrode, and a third sidewall of the top electrode are substantially coplanar.

13. The method for forming the memory device structure as claimed in claim 11 , wherein the removing of the dielectric layer, which is not covered by the etch stop layer, further comprises removing the spacer layer covering a second upper portion of a second sidewall of the etch stop layer.

14. The method for forming the memory device structure as claimed in claim 11 , wherein the providing of the etch stop layer and the spacer layer comprises:
depositing the etch stop layer over the dielectric layer, the bottom electrode, the magnetic tunnel junction stack, and the top electrode;
depositing a spacer material layer over the etch stop layer;
removing the spacer material layer over the top electrode and the second region to form the spacer layer; and
removing the etch stop layer, which is not covered by the spacer layer.

15. The method for forming the memory device structure as claimed in claim 14 , wherein the removing of the spacer material layer over the top electrode and the second region further comprises removing a second upper portion of the etch stop layer over the top electrode and the second region.

16. A memory device structure, comprising:
a substrate having a first region and a second region;
a first etch stop layer over the substrate;
a first dielectric layer over the first etch stop layer and over the first region;
a conductive via passing through the first dielectric layer and the first etch stop layer;
a magnetic tunnel junction cell over the conductive via;
a second etch stop layer surrounding the magnetic tunnel junction cell and a first upper portion of the first dielectric layer, wherein the second etch stop layer is thicker than the first etch stop laye

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Hsing-Hsiang
• Lin Han-Ting
• Yin yu-feng
• Yang Sin-Yi
• Wang Chen-Jung
• Wu Yin-Hao
• Li kun-yi
• Wen Meng-Chieh
• Lin Lin-Ting
• Lin Jiann-Horng
• Chang An-Shen
• Lin Huan-Just

Classifications

• H01L43/10

  Electricity · mapped topic

• H01L43/08 Primary

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic