Memory device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10270028-B1
Application number	US-201715813055-A
Country	US
Kind code	B1
Filing date	Nov 14, 2017
Priority date	Nov 14, 2017
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

A method for manufacturing a memory device, the method includes forming an opening in a dielectric layer; overfilling the opening with a bottom electrode layer; removing a first portion of the bottom electrode layer outside the opening, while leaving a second portion of the bottom electrode layer in the opening to form a bottom electrode; and forming a stack over the bottom electrode, the stack comprising a resistance switching element in contact with the bottom electrode and a top electrode over the resistance switching element.

First claim

What is claimed is:

1. A method for manufacturing a memory device, comprising:
forming a dielectric layer that has a bottom surface above a top surface of a metallization pattern;
forming an opening in the dielectric layer;
overfilling the opening with a bottom electrode layer;
removing a first portion of the bottom electrode layer outside the opening, while leaving a second portion of the bottom electrode layer in the opening to form a bottom electrode in contact with the top surface of the metallization pattern; and
forming a stack over the bottom electrode, the stack comprising a resistance switching element in contact with the bottom electrode and a top electrode over the resistance switching element.

2. The method of claim 1 , wherein the removing the first portion of the bottom electrode layer comprises:
etching back the bottom electrode layer until reaching the dielectric layer, wherein the dielectric layer has higher etch resistance to the etching back than that of the bottom electrode layer.

3. The method of claim 1 , the removing the first portion of the bottom electrode layer comprises:
performing a chemical-mechanical polish process to the bottom electrode layer until reaching the dielectric layer, wherein the dielectric layer has higher resistance to the chemical-mechanical polish process than that of the bottom electrode layer.

4. The method of claim 1 , wherein the forming the stack over the bottom electrode comprises:
forming a resistance switching element layer over the bottom electrode and the dielectric layer; and
removing a first portion of the resistance switching element layer while leaving a second portion of the resistance switching element layer over the bottom electrode to form the resistance switching element.

5. The method of claim 4 , wherein the removing the first portion of the resistance switching element layer comprises:
etching the resistance switching element layer, wherein the dielectric layer has higher etch resistance to the etching the resistance switching element layer than that of the resistance switching element layer.

6. The method of claim 5 , wherein the etching the resistance switching element thins a portion of the dielectric layer.

7. The method of claim 1 , further comprising:
forming a spacer along a sidewall of the stack and over the dielectric layer.

8. The method of claim 7 , wherein the forming the spacer comprises:
forming a spacer layer over and around the stack; and
removing a first portion of the spacer layer while leaving a second portion of the spacer layer around the stack to form the spacer using an etch process, wherein the dielectric layer has higher etch resistance to the etch process than that of the spacer layer.

9. The method of claim 8 , wherein the etch process thins a portion of the dielectric layer.

10. The method of claim 9 , further comprising:
forming an interlayer dielectric layer over the thinned portion of the dielectric layer.

11. A method for manufacturing a memory device, the method comprising:
forming a dielectric layer over an interlayer dielectric layer having an metallization pattern;
patterning the dielectric layer using a patterned photoresist mask to form an opening that exposes the metallization pattern;
forming a bottom electrode in the opening and over the exposed metallization pattern;
forming a stack over the bottom electrode, the stack comprising a resistance switching element in contact with the bottom electrode and a top electrode over the resistance switching element; and
prior to forming the resistance switching element, removing a portion of the bottom electrode to expose the dielectric layer.

12. The method of claim 11 , wherein the forming the stack comprises an etch operation, and the dielectric layer has higher etch resistance to the etch operation than that of the resistance switching element layer.

13. The method of claim 12 , wherein the etch operation thins a portion of the dielectric layer.

14. The method of claim 13 , further comprising:
forming a spacer over the thinned portion of the dielectric layer.

15. The method of claim 11 , wherein the forming the bottom electrode in the opening comprises:
overfilling the opening in the dielectric layer with a bottom electrode layer; and
performing a planarization process to the bottom electrode layer until the dielectric layer is exposed.

16. A memory device, comprising:
a dielectric layer having a stepped top surface;
at least one bottom electrode embedded in the dielectric layer and penetrating through the stepped top surface of the dielectric layer;
at least one resistance switching element over the bottom electrode;
a first spacer on a sidewall of the resistance switching element and in contact with the dielectric layer; and
at least one top electrode over the resistance switching element.

17. The memory device of claim 16 ,
wherein the first spacer is over a first portion of the stepped top surface of the dielectric layer.

18. The memory device of claim 16 , further comprising:
a second spacer on a sidewall of the first spacer, wherein the second spacer is over a second portion of the stepped top surface that is in a position lower than a first portion of the stepped top surface.

19. The memory device of claim 18 , wherein the stepped top surface has a third portion in a position lower than the second portion of the stepped top surface.

20. The memory device of claim 19 , further comprising:
an interlayer dielectric layer in contact with the third portion of the stepped top surface.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tien Hsi-Wen
• Lu Chih-Wei
• Liao Wei-Hao
• Dai Pin-Ren
• Lee Chung-Ju

Classifications

• H01L43/08

  Electricity · mapped topic

• H01L43/12 Primary

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10B61/22

  of the field-effect transistor [FET] type · CPC title