Processes used in fabricating a metal-insulator-semiconductor field effect transistor

Patent metadata

Field	Value
Publication number	US-9508596-B2
Application number	US-201414311165-A
Country	US
Kind code	B2
Filing date	Jun 20, 2014
Priority date	Jun 20, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

During fabrication, a second oxide layer is disposed over a first region and a second region of a structure. The second region includes a first oxide layer between the second oxide layer and an epitaxial layer. The first region corresponds to an active region of a metal-insulator-semiconductor field effect transistor (MISFET), and a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in the first region. The second region corresponds to a termination region of the MISFET. A mask is formed over the second region, and parts of the second oxide layer and the first oxide layer that are exposed through the gaps are removed, thereby exposing the epitaxial layer. Second-type dopant is deposited into the epitaxial layer through the resultant openings in the first and second oxide layers, thereby forming field rings for the MISFET.

First claim

What is claimed is:

1. A process used in fabricating a metal-insulator-semiconductor field-effect transistor (MISFET), said process comprising:
depositing a second oxide layer over a first region and a second region of a structure, said second region comprising a first oxide layer between said second oxide layer and an epitaxial layer, said first region having formed therein a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region, said first region corresponding to an active region of said MISFET and said second region corresponding to a termination region of said MISFET;
forming a mask over said second region, said mask comprising a first plurality of mask elements separated by gaps, said mask further comprising a second plurality of mask elements over said first region, said mask elements in said second plurality separated by a gap;
removing parts of said second oxide layer and said first oxide layer in said second region that are exposed through said gaps in said first plurality of mask elements, thereby exposing said epitaxial layer, and removing parts of said second oxide layer and said first-type dopant source region in said first region that are exposed through said gap in said second plurality of mask elements, thereby exposing said second-type dopant implant region;
depositing second-type dopant into said epitaxial layer through openings formed in said second region by said removing parts of said second oxide layer and said first oxide layer in said second region, thereby forming field rings for said MISFET;
forming a metal layer in contact with said first-type dopant source region and said second-type dopant implant region in said first region; and
forming a passivation layer over said first and second regions, said passivation layer extending into said openings in said second region formed by said removing parts of said second oxide layer and said first oxide layer in said second region.

2. The process of claim 1 , wherein said forming said metal layer comprises:
depositing metal over said first and second regions after said exposing said second-type dopant implant region;
forming a second mask over said metal; and
removing said metal from areas around said second mask to form said metal layer in contact with said first-type dopant source region and said second-type dopant implant region.

3. The process of claim 1 , further comprising, prior to said depositing said second oxide layer:
depositing a polysilicon layer over at least said first region;
removing a portion of said polysilicon layer to expose an area of said first region in which said first-type dopant source region, said second-type dopant body region, and said second-type dopant implant region are subsequently formed; and
after forming said first-type dopant source region and said second-type dopant body region, and before forming said second-type dopant implant region, forming a spacer in contact with a remaining portion of said polysilicon layer and also in contact with said first-type dopant source region.

4. The process of claim 1 , wherein said gaps are uniformly sized and uniformly spaced.

5. The process of claim 1 , wherein each of said gaps is between approximately 0.5 and 0.8 microns in width, and wherein each of said mask elements has a width of approximately 1.8 microns.

6. The MISFET fabricated by the process of claim 1 .

7. A method for fabricating a metal-insulator-semiconductor field-effect transistor (MISFET), said method comprising:
depositing a first oxide layer over an epitaxial layer of a structure;
forming a first mask over said first oxide layer, said first mask defining a second region corresponding to a termination region of said MISFET, said first oxide layer removed from around said first mask to define a first region corresponding to an active region of said MISFET;
after removing said first mask, depositing a polysilicon layer over said first region and said second region;
forming a second mask over said polysilicon layer, said polysilicon layer removed from around said second mask to form an opening in said polysilicon layer in said first region, thereby exposing said epitaxial layer, wherein a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in said epitaxial layer through said opening;
after said second mask is removed, depositing a second oxide layer over said first region and said second region;
forming a third mask over said second region, said third mask comprising a first plurality of mask elements separated by gaps, wherein parts of said second oxide layer and said first oxide layer that are exposed through said gaps are removed, thereby exposing said epitaxial layer, wherein further second-type dopant is deposited into said epitaxial layer through openings formed by removing said parts of said second oxide layer and said first oxide layer, thereby forming field rings for said MISFET;
after said third mask is removed, depositing a metal layer over said first region and said second region;
forming a fourth mask over said metal layer, said metal layer removed from areas around said fourth mask;
after said fourth mask is removed, depositing a passivation layer over said first region and said second region; and
forming a fifth mask over said passivation layer, said passivation layer removed from around said fifth mask to form source and gate bond pad regions for said MISFET.

8. The method of claim 7 , wherein said third mask further comprises a second plurality of mask elements over said first region, said mask elements in said second plurality separated by a gap, said method further comprising removing parts of said second oxide layer and said first-type dopant source region that are exposed through said gap, thereby also exposing said second-type dopant implant region.

9. The method of claim 7 , further comprising, after forming said first-type dopant source region and said second-type dopant body region, and before forming said second-type dopant implant region, forming spacers on each side of said opening, said spacers in contact with a remaining portion of said polysilicon layer and also in contact with said first-type dopant source region.

10. The method of claim 7 , wherein said gaps in said third mask are uniformly sized and uniformly spaced.

11. The method of claim 7 , wherein each of said gaps in said third mask is between approximately 0.5 and 0.8 microns in width, and wherein each of said mask elements has a width of approximately 1.8 microns.

12. The MISFET fabricated by the process of claim 7 .

13. A method for fabricating a metal-insulator-semiconductor field-effect transistor (MISFET), said method comprising:
removing a first oxide layer of a structure from around a first mask to define a first region corresponding to an active region of said MISFET and to expose an epitaxial layer underlying said first oxide layer, said first mask covering a second region corresponding to a termination region of said MISFET;
after removing said first mask and depositing a polysilicon layer over said first and second regions, removing said polysilicon layer from an area in said first region that is not covered by a second mask, thereby forming an opening in said polysilicon layer and exposing said epitaxial layer, wherein a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in said epitaxial layer through said opening;
after removing said second mask and depositing a second oxide layer over said first and second regions, removing said first oxide la

Assignees

• Vishay Siliconix

Inventors

• Tipirneni Naveen
• Pattanayak Deva

Classifications

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D30/665 Primary

  having edge termination structures · CPC title

• H10D30/655

  having edge termination structures · CPC title

• H10D84/0126 Primary

  the components including insulated gates, e.g. IGFETs · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title