Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-11545207-B2
Application number	US-202117387757-A
Country	US
Kind code	B2
Filing date	Jul 28, 2021
Priority date	Sep 3, 2020
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

A semiconductor memory device is provided. The semiconductor memory device can suppress increases in power consumption. As a result, damage to the data normally caused by row hammer problem can be prevented. The semiconductor memory device includes a control unit. The control unit controls a refresh operation for a memory to be performed at any interval, wherein there are a plurality of possible intervals. When read/write access to the memory is required, the control unit controls the refresh operation for the memory to be performed with a shortest interval among the intervals, until a predetermined condition is met.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a control unit, controlling a refresh operation for a memory, wherein when read/write access to the memory is required, the control unit controls the refresh operation for the memory to be performed with a shortest interval among a plurality of intervals, until a predetermined condition is met, and wherein when the predetermined condition is met and no read/write access to the memory is required, the control unit controls the refresh operation for the memory to be performed with an interval, longer than the shortest interval, among the plurality of intervals.

2. The semiconductor memory device as claimed in claim 1 ,
wherein the predetermined condition is that the refresh operation for the memory is performed a predetermined number of times with the shortest interval.

3. The semiconductor memory device as claimed in claim 1 ,
wherein the control unit comprises:
a selector, outputting a refresh trigger signal of any interval among the intervals based on a control signal; and
a circuit unit, when read/write access to the memory is required, generating the control signal and outputting the control signal to the selector, so that the refresh trigger signal of the shortest interval is output from the selector, until the predetermined condition is met.

4. The semiconductor memory device as claimed in claim 1 , further comprising:
a temperature sensor, detecting a temperature of the semiconductor memory device;
wherein when any interval among the intervals corresponds to the temperature of the semiconductor memory device, the control unit controls the refresh operation for the memory to be performed with an interval corresponding to the temperature detected by the temperature sensor.

5. The semiconductor memory device as claimed in claim 4 ,
wherein the control unit comprises:
a first selector, outputting a refresh trigger signal of the interval corresponding to the temperature detected by the temperature sensor among the intervals;
a second selector, outputting the refresh trigger signal of the interval corresponding to the temperature detected by the temperature sensor based on a control signal, or outputting the refresh trigger signal of the shortest interval based on the control signal; and
a circuit unit, when read/write access to the memory is required, generating the control signal and outputting the control signal to the second selector, so that the refresh trigger signal of the shortest interval is output from the second selector, until the predetermined condition is met.

6. The semiconductor memory device as claimed in claim 4 ,
wherein the control unit comprises:
a selector, outputting a refresh trigger signal of the interval corresponding to the temperature detected by the temperature sensor among the intervals based on a control signal; and
a circuit unit, when read/write access to the memory is required, generating the control signal and outputting the control signal to the selector, so that the refresh trigger signal of the shortest interval is output from the selector, until the predetermined condition is met.

7. The semiconductor memory device as claimed in claim 4 ,
wherein the control unit controls the refresh operation for the memory to be performed with the shorter interval if the temperature detected by the temperature sensor is higher.

Assignees

• Winbond Electronics Corp
• Windbond Electronics Corp

Inventors

• Sato Takahiko

Classifications

• G11C11/40611 Primary

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/40626 Primary

  Temperature related aspects of refresh operations · CPC title

• G11C2211/4061

  Calibration or ate or cycle tuning · CPC title