Semiconductor memory device that performs a refresh operation

Patent metadata

Field	Value
Publication number	US-2016125931-A1
Application number	US-201514827686-A
Country	US
Kind code	A1
Filing date	Aug 17, 2015
Priority date	Nov 3, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
a memory circuit including a plurality of memory cells; and a refresh control circuit configured to determine a number of times to perform a target row refresh (TRR) in response to a first mode register set (MRS) code signal, wherein the first MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle for at least two of the memory cells for a period of time when the first mode register set (MRS) code signal is changed due to the temperature change.

2 . The device of claim 1 , wherein the number of times to perform the TRR is set to be smaller than a preset number at a room temperature when a normal refresh cycle is lengthened in response to the first MRS code signal.

3 . The device of claim 1 , wherein the number of times to perform the TRR is set to be greater than a preset number at a room temperature when a normal refresh cycle is shortened in response to the first MRS code signal.

4 . The device of claim 1 , wherein the determined number of the TRR is completed in response to the first MRS code signal before performing the TRR in response to a second MRS code signal input after the first MRS code signal.

5 . The device of claim 4 , wherein, after the determined number of the TRR is completed in response to the first MRS code signal, the TRR is performed in response to the second MRS code signal.

6 . A semiconductor memory device, comprising:
a refresh control circuit configured to set a refresh cycle and a refresh mode according to a temperature change and generate a count enable signal; and a memory circuit configured to perform a normal refresh and a target row refresh (TRR) in a temperature mode set before the temperature change and complete the normal refresh in response to the count enable signal.

7 . The device of claim 6 , wherein the refresh control circuit comprises:
a temperature sensor configured to sense the temperature change and generate a mode register set (MRS) code signal; a TRR count circuit configured to receive the MRS code signal and generate a cycle mode signal corresponding to the MRS code signal; and a refresh cycle signal generation circuit configured to generate the count enable signal in response to the cycle mode signal.

8 . The device of claim 7 , wherein the temperature sensor generates a first MRS code signal when a temperature lower than a room temperature is sensed, a second MRS code signal when the room temperature is sensed, and a third MRS code signal when a temperature higher than the room temperature is sensed.

9 . The device of claim 8 , wherein the TRR count circuit outputs a first cycle mode signal in response to the first MRS code signal, a second cycle mode signal in response to the second MRS code signal, and a third cycle mode signal in response to the third MRS code signal.

10 . The device of claim 8 , wherein the first cycle mode signal has a cycle longer than a cycle of the second cycle mode signal and the cycle of the second cycle mode signal is longer than a cycle of the third cycle mode signal.

11 . The device of claim 7 , wherein the refresh cycle signal generation circuit comprises:
a count unit circuit configured to receive a clock signal and generate a plurality of counting clock signals; and a cycle change circuit configured to generate the count enable signal in response to the plurality of counting clock signals and the cycle mode signal.

12 . The device of claim 11 , wherein the count unit circuit comprises a plurality of dividers.

13 . The device of claim 11 , wherein, when a cycle mode of the cycle mode signal is sampled, the cycle change circuit controls a reset of the counting clock signals to perform the TRR in a corresponding cycle mode.

14 . The device of claim 13 , wherein, when a cycle mode of the cycle mode signal is sampled, the normal refresh and the TRR are performed in response to the count enable signal.

15 . The device of claim 14 , wherein the TRR is performed by a count set to the corresponding cycle mode while the count enable signal is activated.

16 . A semiconductor memory device, comprising:
a memory circuit including a plurality of memory cells; and a refresh control circuit configured to change a refresh cycle of the memory circuit according to a temperature change that occurs while a normal refresh is being performed, wherein a refresh mode is changed responsive to the temperature change after a predetermined time measured from a time of the normal refresh set before the temperature change.

17 . The device of claim 16 , wherein a mode register set (MRS) code signal is used to indicate the temperature change.

18 . The device of claim 17 , wherein the MRS code signal determines a number of times to perform a target row refresh (TRR).

19 . The device of claim 18 , wherein the determined number of the TRR and the normal refresh are performed in a refresh mode set before the temperature change during a predetermined delay time.

20 . The device of claim 18 , wherein the determined number of the TRR is performed during the predetermined delay time.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Doo Suyeon
• Oh Taeyoung
• Kim Namjong
• Park Chulsung

Classifications

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/40626 Primary

  Temperature related aspects of refresh operations · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title