SRAM architecture with bitcells of varying speed and density

Patent metadata

Field	Value
Publication number	US-9953701-B1
Application number	US-201715439899-A
Country	US
Kind code	B1
Filing date	Feb 22, 2017
Priority date	Feb 22, 2017
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

An SRAM with a first bitcell array having a first density and a first access speed, and a second bitcell array having a second density larger than the first density and a second access speed less than the first access speed. The SRAM further includes a first set of wordline drivers coupled to the first bitcell array, a second set of wordline drivers coupled to the second bitcell array, and a row decoder coupled to both the first and second bitcell arrays.

First claim

What is claimed is:

1. A circuit comprising:
a memory comprising:
a first bitcell array having a first density and a first access speed;
a second bitcell array having a second density larger than the first density and a second access speed less than the first access speed;
a first set of wordline drivers coupled to the first bitcell array;
a second set of wordline drivers coupled to the second bitcell array; and
a row decoder coupled to both the first and second bitcell arrays.

2. The circuit as set forth in claim 1 , further comprising:
a processor coupled to the memory to read and write words stored in the memory,
wherein the first bitcell array provides a first set of bits for the words stored in the memory and the second bitcell array provides a second set of bits for the words stored in the memory.

3. The circuit as set forth in claim 2 , wherein the processor accesses the first and second bitcell arrays with a single address space.

4. The circuit as set forth in claim 1 , further comprising a processor accesses the first and second bitcell arrays with a single address space.

5. The circuit as set forth in claim 1 , further comprising:
a first self-timed path coupled to the first bitcell array; and
a second self-timed path coupled to the second bitcell array.

6. The circuit as set forth in claim 5 , wherein the first self-timed path is tuned to the first bitcell array, and the second self-timed path is tuned to the second bitcell array.

7. The circuit as set forth in claim 1 , wherein
the first bitcell array comprises a first plurality of bitcells, each bitcell in the first plurality of bitcells having a first dimension and a second dimension; and
the second bitcell array comprises a second plurality of bitcells, each bitcell in the second plurality of bitcells having a first dimension and a second dimension,
wherein the first dimension of each bitcell in the first plurality of bitcells is larger in value than the first dimension of each bitcell in the second plurality of bitcells, and the second dimension of each bitcell in the first plurality of bitcells is substantially the same in value as the second dimension of each bitcell in the second plurality of bitcells.

8. The circuit as set forth in claim 7 , wherein the memory further comprises wordlines, wherein the first dimension of each bitcell in the first plurality of bitcells is oriented substantially parallel to the wordlines, and the first dimension of each bitcell in the second plurality of bitcells is oriented substantially parallel to the wordlines.

9. The circuit as set forth in claim 7 , further comprising:
a processor coupled to the memory to read and write words stored in the memory,
wherein the first bitcell array provides a first set of bits for the words stored in the memory and the second bitcell array provides a second set of bits for the words stored in the memory.

10. The circuit as set forth in claim 9 , wherein the processor accesses the first and second bitcell arrays with a single address space.

11. The circuit as set forth in claim 10 , further comprising:
a first self-timed path coupled to the first bitcell array; and
a second self-timed path coupled to the second bitcell array.

12. The circuit as set forth in claim 11 , wherein the first self-timed path is tuned to the first bitcell array, and the second self-timed path is tuned to the second bitcell array.

13. A method comprising:
generating a first layout for a first bitcell array having a first density and a first access speed;
generating a second layout for a second bitcell array having a second density larger than the first density and a second access speed less than the first access speed;
generating a third layout for a first set of wordline drivers coupled to the first bitcell array;
generating a fourth layout for a second set of wordline drivers coupled to the second bitcell array;
generating a fifth layout for a row decoder coupled to both the first and second bitcell arrays; and
fabricating one or more masks according to the first, second, third, fourth, and fifth layouts.

14. The method as set forth in claim 13 , further comprising:
generating a sixth layout for a first self-timed path for the first bitcell array;
tuning the sixth layout for the first self-timed path to provide column and row tracking of the first bitcell array;
generating a seventh layout for a second self-timed path for the second bitcell array; and
tuning the seventh layout for the second self-timed path to provide column and row tracking of the second bitcell array.

15. The method as set forth in claim 14 , wherein
generating the first layout for the first bitcell array further comprises tiling instances of a first bitcell, the first bitcell having a first dimension and a second dimension; and
generating the second layout for the second bitcell array further comprises tiling instances of a second bitcell, the second bitcell having a first dimension and a second dimension,
wherein the first dimension of the first bitcell is larger in value than the first dimension of the second bitcell, and the second dimension of the first bitcell is substantially the same in value as the second dimension of the second bitcell.

16. A memory having a butterfly architecture, the memory comprising:
a first bitcell array in a first half of the butterfly architecture of the memory, the first bitcell array comprising a first plurality of bitcells, wherein each bitcell in the first plurality of bitcells has a first dimension and a second dimension;
a second bitcell array in a second half of the butterfly architecture of the memory, the second bitcell array comprising a second plurality of bitcells, wherein each bitcell in the second plurality of bitcells has a first dimension and a second dimension, wherein the first dimension of the bitcells in the first plurality of bitcells is larger in value than the first dimension of the bitcells in the second plurality of bitcells, and the second dimension of the bitcells in the first plurality of bitcells is substantially the same in value as the second dimension of the bitcells in the second plurality of bitcells;
a first set of wordline drivers coupled to the first bitcell array;
a second set of wordline drivers coupled to the second bitcell array; and
a row decoder coupled to both the first and second bitcell arrays.

17. The memory as set forth in claim 16 , further comprising:
a first self-timed path coupled to the first bitcell array; and
a second self-timed path coupled to the second bitcell array.

18. The memory as set forth in claim 17 , wherein the first self-timed path is tuned to the first bitcell array, and the second self-timed path is tuned to the second bitcell array.

19. The memory as set forth in claim 16 , wherein the row decoder is in a central portion of the butterfly architecture of the memory.

20. The memory as set forth in claim 19 , further comprising:
a first self-timed path in the first half of butterfly architecture of the memory and coupled to the first bitcell array; and
a second self-timed path in the second half of butterfly architecture of the memory and coupled to the second bitcell array.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Bohra Fakhruddin Ali
• Gupta Lalit
• Dwivedi Shri Sagar
• Dasani Jitendra

Classifications

• G11C11/413 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C11/418

  Address circuits · CPC title