Data processing device and method for processing an interrupt

Patent metadata

Field	Value
Publication number	US-11544103-B2
Application number	US-202017038183-A
Country	US
Kind code	B2
Filing date	Sep 30, 2020
Priority date	Oct 7, 2019
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

A data processing device is described including one or more processors implementing a plurality of data processing entities, one or more software interrupt nodes and an access register for each software interrupt node. The access register specifies which one or more data processing entities of the plurality of data processing entities is/are each allowed to, as interrupt source data processing entity, trigger an interrupt service request on the software interrupt node for another one of the plurality of data processing entities as an interrupt target processing entity. Each software interrupt node is configured to forward an interrupt service request triggered by an interrupt source data processing entity which is allowed to trigger an interrupt service request on the software interrupt node to an interrupt target processing entity.

First claim

What is claimed is:

1. A data processing device comprising:
one or more processors implementing a plurality of data processing entities;
a plurality of software interrupt nodes; and
a plurality of access registers, wherein each access register is operably coupled to a respective one of the plurality of software interrupt nodes, and wherein each access register is configured to specify which one or more data processing entities of the plurality of data processing entities is respectively allowed to, as an interrupt source data processing entity, trigger an interrupt service request on the respective software interrupt node for another one of the plurality of data processing entities as an interrupt target processing entity; and
wherein each software interrupt node is configured to forward the interrupt service request triggered by the interrupt source data processing entity which is allowed to trigger the interrupt service request on the software interrupt node to the interrupt target processing entity.

2. The data processing device of claim 1 , wherein the plurality of software interrupt nodes are nodes configured to receive the interrupt requests from the plurality of data processing entities, generate the interrupt service requests for the interrupt requests and forward the interrupt service requests to the plurality of data processing entities.

3. The data processing device of claim 1 , further comprising, for each software interrupt node, access circuitry configured to control access to the software interrupt node for triggering interrupt service requests on the software interrupt node.

4. The data processing device of claim 3 , wherein the access circuitry is configured to, on the software interrupt node to data processing entities specified by the access register for the software interrupt node, restrict access to the software interrupt node for triggering interrupt service requests.

5. The data processing device of claim 1 , further comprising a message transmission register for each software interrupt node, the message transmission register configured to receive and store data to be transmitted from an interrupt source data processing entity to an interrupt target data processing entity.

6. The data processing device of claim 5 , further comprising a protection circuit configured to prevent overwriting of the message transmission register by another interrupt source data processing entity until the interrupt source data processing entity allows overwriting of the message transmission register.

7. The data processing device of claim 1 , further comprising an interrupt router comprising the plurality of software interrupt nodes.

8. The data processing device of claim 1 , wherein each processor of the one or more processors has a plurality of processor cores.

9. The data processing device of claim 8 , wherein at least some of the processor cores are each configured to implement a plurality of virtual machines.

10. The data processing device of claim 1 , wherein the data processing entities comprise processing cores, virtual machines implemented on one or more processors or processing cores and/or tasks implemented on one or more processors or processing cores.

11. The data processing device of claim 1 , wherein for each software interrupt node, a plurality of data processing entities are configured to trigger an interrupt service request on the software interrupt node.

12. The data processing device of claim 1 , further comprising a target register for each software interrupt node, the target register configured to specify the interrupt target processing entity for the software interrupt node.

13. The data processing device of claim 12 , wherein the software interrupt node is configured to forward the interrupt service request to the interrupt target processing entity specified by the target register.

14. A method for processing an interrupt, comprising:
allowing, based on a dedicated access register, a data processing entity of a plurality of data processing entities implemented by one or more processors to trigger an interrupt request on a software interrupt node, wherein the access register specifies which one or more data processing entities is allowed to trigger an interrupt service request on the software interrupt node for a plurality of software interrupt nodes and a plurality of dedicated access registers, wherein each of the dedicated access registers is operably coupled to one of the software interrupt nodes, respectively;
receiving the interrupt request trigger signal for the software interrupt node from the data processing entity having the access register;
establishing an interrupt service request in response to the received interrupt request trigger signal; and
forwarding the established interrupt service request to another one of the data processing entities.

Assignees

• Infineon Technologies Ag

Inventors

• Wirrer Gerhard
• Hellwig Frank
• Kumar Varun

Classifications

• G06F9/327

  for interrupts · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• G06F9/546

  Message passing systems or structures, e.g. queues · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F2009/45562

  Creating, deleting, cloning virtual machine instances · CPC title