Directed interrupt virtualization with fallback

Patent metadata

Field	Value
Publication number	US-11243791-B2
Application number	US-202016789600-A
Country	US
Kind code	B2
Filing date	Feb 13, 2020
Priority date	Feb 14, 2019
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One of the processors receives from a bus attachment device an interrupt signal issued by a bus connected module. A logical processor ID resulting from a translation of an interrupt target ID provided with the interrupt signal is used to address the receiving processor directly. The receiving processor checks whether interrupt target ID identifies the receiving processor as a target processor of the interrupt signal. If the receiving processor is not the target processor, the interrupt signal is forwarded for handling by the guest operating system using broadcasting.

First claim

What is claimed is:

1. A computer program product for providing an interrupt signal to a guest operating system executed using one or more processors of a plurality of processors of a computer system assigned for usage by the guest operating system, the computer program product comprising:
at least one computer readable storage medium readable by at least one processing circuit and storing instructions for performing a method comprising:
receiving, by a processor of the plurality of processors assigned for usage by the guest operating system, an interrupt signal from a bus connected module, the processor being addressed as a target of the interrupt signal directly by using a logical processor ID of the processor, the interrupt signal being received with an interrupt target ID identifying the processor assigned for usage by the guest operating system as a target processor for handling the interrupt signal;
checking, by the processor, whether the processor is the target processor identified by the interrupt target ID, the checking comprising performing a comparison of the interrupt target ID with a current interrupt target ID temporarily assigned to the processor; and
accepting, based on the checking indicating a match of the interrupt target ID with the current interrupt target ID, the interrupt signal for handling by the processor.

2. The computer program product of claim 1 , wherein the method further comprises broadcasting the interrupt signal to remaining processors of the plurality of processors for handling of the interrupt signal by the guest operating system.

3. The computer program product of claim 1 , wherein the receiving the interrupt signal further comprises receiving the interrupt signal with a logical partition ID identifying a logical partition to which the guest operating system is assigned, and wherein the checking further comprises comparing the logical partition ID with a current logical partition ID temporarily assigned to the processor, wherein the accepting is performed based on a match of the logical partition ID with the current logical partition ID.

4. The computer program product of claim 3 , wherein the method further comprises broadcasting the interrupt signal to remaining processors of the plurality of processors for handling of the interrupt signal by the guest operating system, the broadcasting being limited to the remaining processors of the plurality of processors assigned to the logical partition ID.

5. The computer program product of claim 4 , wherein the receiving the interrupt signal further comprises receiving the interrupt signal with an interrupt subclass ID identifying an interrupt subclass to which the interrupt signal is assigned, and wherein the broadcasting is limited to the remaining processors assigned to the interrupt subclass ID.

6. The computer program product of claim 1 , wherein the logical processor ID is based on a mapping of the interrupt target ID.

7. The computer program product of claim 1 , wherein the receiving is performed based on a running indicator indicating that the target processor identified by the interrupt target ID is scheduled for usage by the guest operating system.

8. The computer program product of claim 1 , wherein the receiving is performed based on an interrupt blocking indicator indicating that the target processor identified by the interrupt target ID is currently not blocked from receiving interrupt signals.

9. The computer program product of claim 1 , wherein the receiving is performed based on a direct signaling indicator indicating that the target processor is to be addressed directly.

10. The computer program product of claim 1 , wherein the receiving is performed based on a running indicator indicating that the target processor identified by the interrupt target ID is scheduled for usage by the guest operating system, based on an interrupt blocking indicator indicating that the target processor identified by the interrupt target ID is currently not blocked from receiving interrupt signals, and based on a direct signaling indicator indicating that the target processor is to be addressed directly.

11. A computer system for providing an interrupt signal to a guest operating system, the computer system comprising:
a plurality of processors assigned for usage by the guest operating system, wherein the guest operating system is executed using one or more processors of the plurality of processors assigned for usage by the guest operating system, the computer system configured to perform a method, said method comprising:
receiving, by a processor of the plurality of processors assigned for usage by the guest operating system, an interrupt signal from a bus connected module, the processor being addressed as a target of the interrupt signal directly by using a logical processor ID of the processor, the interrupt signal being received with an interrupt target ID identifying the processor assigned for usage by the guest operating system as a target processor for handling the interrupt signal;
checking, by the processor, whether the processor is the target processor identified by the interrupt target ID, the checking comprising performing a comparison of the interrupt target ID with a current interrupt target ID temporarily assigned to the processor; and
accepting, based on the checking indicating a match of the interrupt target ID with the current interrupt target ID, the interrupt signal for handling by the processor.

12. The computer system of claim 11 , wherein the receiving the interrupt signal further comprises receiving the interrupt signal with a logical partition ID identifying a logical partition to which the guest operating system is assigned, and wherein the checking further comprises comparing the logical partition ID with a current logical partition ID temporarily assigned to the processor, wherein the accepting is performed based on a match of the logical partition ID with the current logical partition ID.

13. The computer system of claim 11 , wherein the receiving is performed based on a running indicator indicating that the target processor identified by the interrupt target ID is scheduled for usage by the guest operating system.

14. The computer system of claim 11 , wherein the receiving is performed based on an interrupt blocking indicator indicating that the target processor identified by the interrupt target ID is currently not blocked from receiving interrupt signals.

15. The computer system of claim 11 , wherein the receiving is performed based on a direct signaling indicator indicating that the target processor is to be addressed directly.

16. A computer-implemented method of providing an interrupt signal to a guest operating system executed using one or more processors of a plurality of processors of a computer system assigned for usage by the guest operating system, the computer-implemented method comprising:
receiving, by a processor of the plurality of processors assigned for usage by the guest operating system, an interrupt signal from a bus connected module, the processor being addressed as a target of the interrupt signal directly by using a logical processor ID of the processor, the interrupt signal being received with an interrupt target ID identifying the processor assigned for usage by the guest operating system as a target processor for handling the interrupt signal;
checking, by the processor, whether the processor is the target processor identified by the interrupt target ID, the checking comprising performing a comparison of the interrupt target ID with a current interrupt target ID temporarily

Assignees

• IBM

Inventors

• Raisch Christoph
• Kraemer Marco
• Schmidt Donald William
• Nerz Bernd
• Driever Peter Dana

Classifications

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• G06F9/45545 Primary

  Guest-host, i.e. hypervisor is an application program itself, e.g. VirtualBox · CPC title

• G06F2213/24

  Interrupt · CPC title

• G06F9/45533

  Hypervisors; Virtual machine monitors · CPC title