Virtual machine monitor interrupt support for computer processing unit (CPU)

Patent metadata

Field	Value
Publication number	US-10248595-B2
Application number	US-201715673943-A
Country	US
Kind code	B2
Filing date	Aug 10, 2017
Priority date	Aug 10, 2017
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can include a memory that includes instructions to execute operations of a processor component, a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to execute the plurality of VMs. The processor can receive interrupt requests (interrupt) as service requests in parallel, which can be executed by the VMM or any one or more of the plurality of VMs to execute VM applications on a dedicated instance of a guest operating system for a task. The processor can further determine whether to grant an interrupt request to the VMM and the VMs based on predetermined criteria, including a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status of each of the component.

First claim

What is claimed is:

1. A system, comprising:
a processor component comprising a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to control the plurality of VMs, wherein the processor component is configured to:
receive a plurality of interrupt requests that correspond to one or more of: the VMM/hypervisor or the plurality of VMs; and
determine whether to grant an interrupt request of the plurality of interrupt requests to the VMM/hypervisor and the plurality of VMs based on a set of predetermined criteria,
wherein the processor component is further configured to determine current statuses of interrupt priority schemes at the VMM/hypervisor and the plurality of VMs as part of the set of predetermined criteria.

2. The system of claim 1 , wherein the VMM/hypervisor and the plurality of virtual machines (VMs) respectively comprise a interrupt control register (ICR) and a previous context and execution information (PCXI) register.

3. The system of claim 2 , wherein the set of predetermined criteria comprises one or more of: a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status.

4. The system of claim 1 , wherein the processor component further comprises a processor status register, comprising an extended processor status word (ePSW), and an additional register comprising the interrupt control register (ICR) configuration control (ICR CTRL) that comprises a plurality of responses to various interrupt conditions related to the VMM/hypervisor and the plurality of VMs.

5. The system of claim 1 , wherein the plurality of interrupt requests comprises a plurality of VM service requests corresponding to one or more VM applications.

6. The system of claim 1 , wherein the processor component is further configured to directly forward one or more interrupt requests of the plurality of interrupt requests to a VM of the plurality of VMs while the VM is concurrently under execution, and wherein the VM is further configured to receive the one or more interrupt requests without a VMM call from the VMM/hypervisor.

7. The system of claim 1 , wherein the processor component further comprises a decision logic component configured to determine whether a first VM of the plurality of VMs is configured to be interrupted by a service request received from a second VM of the plurality of VMs based on one or more conditions configured by the VMM/hypervisor.

8. The system of claim 7 , wherein the VMM/hypervisor is further configured to define the one or more conditions for the decision logic component, wherein the one or more conditions comprise priority thresholds comprising: a pending interrupt number associated with the VMM/hypervisor and the plurality of VMs respectively, a current central processing unit (CPU) priority number associated with the VMM/hypervisor and the plurality of VMs respectively, and one or more additional priority thresholds for determining whether a first VM is able to be interrupted directly by an interrupt mapped to a second VM in response to the processor component operating in a VM mode.

9. An apparatus, comprising:
a processor comprising a memory that includes instructions to execute operations, a plurality of interfaces and a bus, wherein the bus is configured to communicatively couple the memory and the plurality of interfaces to a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor, and to communicate data related to a plurality of interrupt requests among the plurality of VMs and the VMM/hypervisor to a decision logic component;
wherein the processor is configured to determine whether to grant an interrupt request of the plurality of interrupt requests to or from the VMM/hypervisor and the plurality of VMs based on a set of predetermined criteria, and wherein the plurality of interrupt requests comprises a plurality of winning service requests that result from different interrupt priority schemes at the VMM and the plurality of VMs.

10. The apparatus of claim 9 , wherein the set of predetermined criteria comprises a mode of operation of the processor from a set of modes comprising a VM mode and a VMM/hypervisor mode, and wherein the processor is further configured to directly grant the interrupt request and trigger an interrupt service routine (ISR) at a VM of the plurality of VMs in response to being in the VM mode.

11. The apparatus of claim 9 , wherein the processor is further configured to trigger an ISR at a VM of the plurality of VMs in response to the interrupt request as a winning service request based on first priority levels of applications being executed by the plurality of VMs and second priority levels of the plurality of VMs defined by the VMM/hypervisor.

12. The apparatus of claim 9 , further comprising:
a processor status register, comprising an extended processor status word (ePSW), coupled to the decision logic component, and configured to provide the ePSW to the decision logic component; and
an additional register, comprising an interrupt control register (ICR) configuration control (ICR CTRL) that comprises a plurality of responses to various interrupt conditions related to the VMM/hypervisor and the plurality of VMs, coupled to the decision logic component, and configured to provide the ICR CTRL to the decision logic component.

13. The apparatus of claim 12 , wherein the ePSW indicates whether the VMM/hypervisor and one or more VMs of the plurality of VMs is in a busy state, and identifies the one or more VMs in the busy state.

14. The apparatus of claim 12 , wherein the decision logic component is configured to determine whether a first VMx of the plurality of VMs is configured to be interrupted by a service request received from a second VMy of the plurality of VMs based on the various interrupt conditions, and determine the responses to the various conditions based on a comparison with priority thresholds.

15. The apparatus of claim 14 , wherein the priority thresholds comprise: a pending interrupt number associated with the VMM/hypervisor and the plurality of VMs respectively, a current central processing unit (CPU) priority number associated with the VMM/hypervisor and the plurality of VMs respectively, and one or more additional priority thresholds for determining whether a first VM is able to be interrupted directly by an interrupt mapped to a second VM in response to the processor operating in a VM mode or a VMM/hypervisor mode of operation.

16. A method comprising:
receiving, via one or more processors, an interrupt the corresponds to at least one of: a VMM/hypervisor or a plurality of VMs;
generating, via the one or more processors, a determination of whether to grant the interrupt to the VMM/hypervisor and the plurality of VMs based on a set of predetermined criteria;
determining current results of a plurality of interrupt priority schemes performed at the VMM/hypervisor and the plurality of VMs based on information from a central processing unit (CPU) interrupt control registers (ICRs) and previous context and execution information (PCXIs) registers at the VMM/hypervisor and the plurality of virtual machines (VMs); and
communicating, via a bus communicatively coupled to the one or more processors, the VMM/hypervisor and the plurality of VMs, the interrupt based on the determination.

17. The method of claim 16 , wherein the operations further comprise:
in response to operating in a VM mode instead of a VMM/hypervisor mode, directly forwarding, via the bus, the interrupt to a VM of the plurality of VMs while the

Assignees

• Infineon Technologies Ag

Inventors

• Hellwig Frank
• Wirrer Gerhard
• Farrall Glenn
• Hastie Neil

Classifications

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F13/34 Primary

  with priority control · CPC title

• G06F9/4818

  Priority circuits therefor · CPC title

• G06F2009/45591

  Monitoring or debugging support · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title