Timing circuit for locking a voltage controlled oscillator to a high frequency by use of low frequency quotients and resistor to switched capacitor matching

Patent metadata

Field	Value
Publication number	US-11539328-B2
Application number	US-202017095085-A
Country	US
Kind code	B2
Filing date	Nov 11, 2020
Priority date	Jul 15, 2020
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

Devices, systems, and methods for locking a voltage controlled oscillator (VCO) at a high frequency may include use of a VCO and an integrator, which generates and outputs a control signal to the VCO, based on an inverting signal and a reference signal. The control signal locks the VCO to a high frequency signal (FH). A frequency divider is coupled to the VCO, receives FH from the VCO, divides FH by a factor “F”, and outputs a low frequency signal (FL). A switched capacitor resistor circuit (SCRC) is coupled to the frequency divider and the integrator. The SCRC receives FL from the frequency divider and generates the inverting signal. An integrating capacitor is coupled across an inverting and an output terminal of op-amp in the integrator. The output of the op-amp provides an integrator signal, which may be (optionally) filtered to produce the control signal.

First claim

What is claimed is:

1. A circuit, locking a voltage controlled oscillator at a high frequency, comprising:
a voltage controlled oscillator (VCO); and
an integrator operable to generate and output a control signal to the VCO;
wherein the integrator is operable to receive an inverting signal and a reference signal;
wherein the control signal locks the VCO to a high frequency signal based upon the inverting signal;
wherein the inverting signal is received in response to a low frequency signal; and
wherein the low frequency signal is a quotient of the high frequency signal.

2. The circuit of claim 1 , further comprising:
a frequency divider, coupled to the VCO, operable to:
receive the high frequency signal from the VCO;
divide the high frequency signal by a factor “F”; and
output, based on the dividing of the high frequency signal, the low frequency signal.

3. The circuit of claim 2 ,
wherein the frequency divider further comprises:
two or more flip-flop stages operable to successively divide the high frequency signal into the low frequency signal.

4. The circuit of claim 3 ,
wherein the low frequency signal has a given period T FL ; and
wherein during the given period T FL , ripples are generated by the integrator in the control signal and the VCO generates jitter in a frequency of the high frequency signal.

5. The circuit of claim 4 ,
wherein the jitter distributes the high frequency signal over a wider frequency band; and
wherein an amplitude of an individual frequency component of the high frequency signal is reduced.

6. The circuit of claim 2 ,
wherein F equals thirty-two.

7. The circuit of claim 1 ,
wherein a period of the low frequency signal is generated as a given number of periods of the high frequency signal (T FH );
wherein the low frequency signal has a given period TEL; and
wherein the circuit further comprises:
a frequency divider operable to output the low frequency signal; and
a switched capacitor resistor circuit (SCRC), coupled to the frequency divider and the integrator, operable to:
receive the low frequency signal from the frequency divider; and
based on a frequency of the low frequency signal, generates the inverting signal.

8. The circuit of claim 1 , further comprising:
a switched capacitor resistor circuit (SCRC) coupled to the integrator;
wherein the SCRC is operable to:
receive the low frequency signal;
generate, in response to a frequency of the low frequency signal, the inverting signal by:
during a first phase of a given period T FL of the low frequency signal, coupling a switched capacitor to a ground potential; and
charging the switched capacitor by a second reference signal; and

during a second phase of the given period T FL of the low frequency signal, coupling the switched capacitor to the integrator; and
outputting the inverting signal to the integrator;

wherein the inverting signal comprises an inverting voltage signal and an inverting current signal; and
wherein the integrator is operable to:
force the inverting voltage signal to equal the reference signal; and

wherein the inverting current signal results in the integrator generating the control signal.

9. The circuit of claim 8 ,
wherein the integrator further comprises:
an op-amp further comprising:
an inverting node;
a non-inverting node; and
an output node; and

an integrating capacitor coupled to the non-inverting node;
wherein the integrating capacitor has an integrator capacitance;

wherein the switched capacitor has a switched capacitance;
wherein the VCO is coupled to the output node;
wherein the inverting signal further comprises an inverting voltage signal and an inverting current signal; and
wherein the inverting voltage signal is provided at the inverting node;
wherein, during the second phase, the inverting current signal charges the integrating capacitor;
wherein the reference signal is provided at the non-inverting node;
wherein the reference signal equals the second reference signal;
wherein the reference signal is generated from a supply voltage; and
wherein the control signal is generated based upon a product of the supply voltage times the switched capacitance and the product being divided by the integrator capacitance.

10. The circuit of claim 9 ,
wherein the SCRC further comprises:
a first switch for selectively coupling a top terminal of the switched capacitor, via a terminal A, to a ground potential, and via a terminal B, to the supply voltage;
a second switch for selectively coupling a bottom terminal of the switched capacitor, via a terminal C, to the integrator and via a terminal D, to a reference circuit; and
a discharge resistor R coupled at a bottom terminal to ground and at a top terminal to the inverting node and to terminal C of the second switch;

wherein the reference circuit further comprises:
a first reference resistor coupled between the supply voltage and to the non-inverting node; and
a second reference resistor coupled between the non-inverting node and the ground; and

wherein during the first phase of the given period T FL , a discharge current flows from the integrating capacitor to ground via the discharge resistor R.

11. A circuit comprising:
a voltage controlled oscillator (VCO);
a reference circuit;
an integrator including an op-amp including:
an inverting node,
a non-inverting node coupled to the reference circuit, and
an output node coupled to the VCO, and
an integrator capacitor coupled to the non-inverting node and the output node;

a switched capacitor resistor circuit (SCRC) including:
a first switch,
a second switch, and
a switched capacitor coupled to the first switch and the second switch,
the switched capacitor being selectively coupled:
at a top terminal, to a ground potential or a supply voltage using the first switch;
at a bottom terminal, to the inverting node or to the reference circuit using the second switch; and

a discharge resistor coupled between the ground potential and the inverting node,

wherein charging and discharging of the integrator capacitor results in the integrator generating an integrated signal used to generate a control signal provided to the VCO, the VCO is locked to and outputs a high frequency signal based on the control signal.

12. The circuit of claim 11 , further comprising:
a frequency divider, coupled to the VCO and the SCRC; and
wherein the frequency divider generates a low frequency signal based on the high frequency signal received from the VCO.

13. The circuit of claim 12 ,
wherein the frequency divider further comprises:
“N” flip-flop stages, operable to successively divide the high frequency signal; and
wherein, the integrator is operable to generate ripples in the control signal; and
wherein, based on the ripples in the control signal, the VCO is operable to generate jitter in a frequency of the high frequency signal.

14. The circuit of claim 13 ,
wherein N equals five stages;
wherein the ripples in the control signal are approximately fifteen millivolts (15 mV) peak-to-peak; and
wherein the jitter in the frequency of the high frequency signal is approximately fifteen megahertz (15 MHz).

15. The circuit of claim 12 , further comprising:
a filter operable to:
receive the integrated signal from the integrator;
filter the integrated signal to generate the control signal; and
output the control signal to the VCO.

16. The circuit of claim 12 ,
wherein a period of a low frequency signal is proportional to a resistance of a discharge resistor ti

Assignees

• Semiconductor Components Ind Llc

Inventors

• Vander Voorde Lucas Emiel Elie
• Plojhar Jan

Classifications

• H03B5/1237 Primary

  comprising means for varying the frequency of the generator · CPC title

• H03K5/00006 Primary

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• H03B5/129

  the parameter being a bias voltage or a power supply · CPC title

• H03B5/1271

  the frequency being controlled by a control current, i.e. current controlled oscillators · CPC title

• H03L7/00

  Automatic control of frequency or phase; Synchronisation · CPC title