Resistor-capacitor oscillator (RCO) with digital calibration and quantizaton noise reduction

Patent metadata

Field	Value
Publication number	US-11115036-B1
Application number	US-202016991882-A
Country	US
Kind code	B1
Filing date	Aug 12, 2020
Priority date	Aug 12, 2020
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

An oscillator including a switched capacitor configured to generate a sawtooth or ramp voltage in response to a switched capacitor drive signal; a low pass filter (LPF) configured to filter the sawtooth or ramp voltage to generate a filtered voltage; a reference voltage generator configured to generate a reference voltage; an integrator configured to integrate a difference between the sawtooth or ramp voltage and the reference voltage to generate a frequency control signal; a voltage controlled oscillator (VCO) configured to generate a first clock based on the frequency control signal; a frequency divider configured to frequency divide the first clock to generate a second clock; and a switched capacitor driver configured to generate the switched capacitor drive signal in response to the second clock. The oscillator may also include a switched capacitor sampler to sample the sawtooth or ramp voltage, wherein the filtered voltage is based on the sampled voltage.

First claim

What is claimed:

1. An apparatus, comprising:
a switched capacitor having
a current source,
a first switching device,
a first capacitor coupled in series with the current source and the first switching device between a first voltage rail and a second voltage rail, and
a second switching device coupled in parallel with the first capacitor;

a low pass filter (LPF) including an input coupled to an output of the switched capacitor;
a reference voltage generator;
an integrator including a first input coupled to an output of the LPF and a second input coupled to an output of the reference voltage generator;
a voltage controlled oscillator (VCO) including an input coupled to an output of the integrator;
a first frequency divider including an input coupled to an output of the VCO; and
a switched capacitor driver including an input coupled an output of the first frequency divider, wherein the switched capacitor includes an input coupled to an output of the switched capacitor driver.

2. The apparatus of claim 1 , wherein the switched capacitor comprises a second capacitor coupled in parallel with the first switching device coupled in series the first capacitor.

3. The apparatus of claim 1 , wherein the output of the switched capacitor driver is coupled to the first and second switching devices.

4. The apparatus of claim 1 , wherein the reference voltage generator comprises a current source coupled in series with a resistor between a first voltage rail and a second voltage rail.

5. The apparatus of claim 1 , wherein the LPF comprises:
a series resistor; and
a shunt capacitor.

6. The apparatus of claim 1 , wherein the integrator comprises:
an operational amplifier, wherein a negative input of the operational amplifier includes the first input of the integrator, wherein a positive input of the operational amplifier includes the second input of the integrator, and wherein an output of the operational amplifier includes the output of the integrator; and
a capacitor coupled between the output and the negative input of the operational amplifier.

7. The apparatus of claim 6 , wherein the integrator further comprises a resistor coupled in series with the capacitor between the output and the negative input of the operational amplifier.

8. The apparatus of claim 1 , wherein the VCO comprises a ring oscillator (RO).

9. The apparatus of claim 1 , wherein the first frequency divider comprises a fractional divider.

10. The apparatus of claim 1 , wherein the first frequency divider comprises:
a multi-modulus divider, wherein a first input of the multi-modulus divider is the input of the first frequency divider, and an output of the multi-modulus divider is the output of the first frequency divider; and
a sequence generator including a first input coupled to the output of the multi-modulus divider, a second input to receive a frequency divider ratio control signal, and an output coupled a second input of the multi-modulus divider.

11. The apparatus of claim 10 , wherein the sequence generator comprises a sigma-delta modulator.

12. The apparatus of claim 10 , further comprises a frequency measurement circuit including a first input coupled to the output of the multi-modulus divider, a second input to receive a reference clock, and an output to generate the frequency divider ratio control signal.

13. The apparatus of claim 1 , wherein the switched capacitor driver comprises a non-overlapping clock including first and second outputs, wherein the output of the switched capacitor driver comprises the first and second outputs to generate first and second non-overlapping clocks, and wherein the first and second outputs are coupled to the switched capacitor.

14. An apparatus, comprising:
a switched capacitor;
a low pass filter (LPF) including an input coupled to an output of the switched capacitor;
a reference voltage generator;
an integrator including a first input coupled to an output of the LPF and a second input coupled to an output of the reference voltage generator;
a voltage controlled oscillator (VCO) including an input coupled to an output of the integrator;
a first frequency divider including an input coupled to an output of the VCO,
a switched capacitor driver including an input coupled an output of the first frequency divider, wherein the switched capacitor includes an input coupled to an output of the switched capacitor driver; and
a switched capacitor sampler including a first input coupled to the output of the switched capacitor and an output coupled to the input of the LPF.

15. The apparatus of claim 14 , wherein the switched capacitor sampler comprises:
a first switching device coupled between the first input of the switched capacitor sampler and an internal node;
a capacitor coupled between the internal node and a voltage rail; and
a second switching device coupled between the internal node and an output of the switched capacitor sampler.

16. The apparatus of claim 14 , comprising a switched capacitor sampler driver including an input coupled to the output of the switched capacitor driver, and an output coupled to a second input of the switched capacitor sampler.

17. The apparatus of claim 16 , wherein the switched capacitor sampler driver comprises:
a second frequency divider including an input coupled to the output of the switched capacitor driver; and
a non-overlapping clock including a first input coupled to an output of the second frequency divider, and first and second outputs to generate non-overlapping clocks for first and second switching devices in the switched capacitor sampler.

18. The apparatus of claim 17 , wherein the non-overlapping clock is configured to assert signals at the first and second outputs in response to a start signal.

19. An apparatus, comprising:
a switched capacitor configured to generate a sawtooth or ramp voltage in response to a switched capacitor drive signal;
a low pass filter (LPF) configured to filter the sawtooth or ramp voltage to generate a filtered voltage;
a reference voltage generator configured to generate a reference voltage;
an integrator configured to integrate a difference between the sawtooth or ramp voltage and the reference voltage to generate a frequency control signal;
a voltage controlled oscillator (VCO) configured to generate a first clock based on the frequency control signal;
a frequency divider configured to frequency divide the first clock to generate a second clock; and
a switched capacitor driver configured to generate the switched capacitor drive signal in response to the second clock.

20. The apparatus of claim 19 , comprising a switched capacitor sampler configured to generate a sampled voltage of the sawtooth or ramp voltage, wherein the LPF is configured to filter the sampled voltage to generate the filtered voltage.

21. The apparatus of claim 20 , wherein the switched capacitor sampler comprises:
a sampling capacitor to store the sampled voltage;
a first switching device configured to:
route the sawtooth or ramp voltage to the sampling capacitor to generate the sampled voltage during a first time interval; and
decouple the sawtooth or ramp voltage from the sampling capacitor during a second time interval; and

a second switching device configured to:
decouple the LPF from the sampling capacitor during the first time interval; and
provide the sampled voltage to the LPF during the second time interval.

22. The apparatus of claim 21 , wherein the first and s

Assignees

• Qualcomm Inc

Inventors

• Zhao Shitong
• Wang Kevin Jia-Nong
• Sivakumar Shyam
• Bhatta Debesh

Classifications

• H03L7/0992

  comprising a counter or a frequency divider · CPC title

• H03L7/00 Primary

  Automatic control of frequency or phase; Synchronisation · CPC title

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03L7/148

  said digital means comprising a counter or a divider · CPC title

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title