Display device having first transistor, second transistor, and third transistor disposed on different layers

Patent metadata

Field	Value
Publication number	US-11538879-B2
Application number	US-202016952787-A
Country	US
Kind code	B2
Filing date	Nov 19, 2020
Priority date	Feb 12, 2020
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A display device includes an organic light emitting diode, a first transistor driving the organic light emitting diode, a second transistor transmitting a data signal to the first transistor, a third transistor transmitting a first power voltage to the first transistor, wherein a semiconductor pattern of the first transistor is disposed over a semiconductor pattern of the second transistor, a semiconductor pattern of the third transistor is disposed over the semiconductor pattern of the first transistor, a lower transistor insulating film is disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the second transistor, and an upper transistor insulating film is disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor.

First claim

What is claimed is:

1. A display device, comprising:
an organic light emitting diode;
a first transistor that receives a data signal from a data line and controls a driving current to drive the organic light emitting diode;
a second transistor electrically connected to the data line and a first source or drain electrode of the first transistor, the second transistor transmitting the data signal received from the data line to the first transistor;
a third transistor electrically connected to a first power voltage line and the first source or drain electrode of the first transistor, the third transistor transmitting a first power voltage from the first power voltage line to the first transistor, wherein
a semiconductor pattern of the first transistor is disposed over a semiconductor pattern of the second transistor, and
a semiconductor pattern of the third transistor is disposed over the semiconductor pattern of the first transistor;

a lower transistor insulating film disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the second transistor; and
an upper transistor insulating film disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor.

2. The display device of claim 1 , further comprising:
a fourth transistor electrically connected to a gate electrode and a second source or drain electrode of the first transistor,
wherein a semiconductor pattern of the fourth transistor is disposed between the semiconductor pattern of the second transistor and the semiconductor pattern of the third transistor.

3. The display device of claim 2 , further comprising:
a sub-gate insulating film overlapping the gate electrode of the first transistor and not overlapping a gate electrode of the fourth transistor,
wherein a thickness between the gate electrode of the first transistor and a channel region is greater than a thickness between the gate electrode of the fourth transistor and a channel region.

4. The display device of claim 2 , further comprising:
a fifth transistor electrically connected to the gate electrode of the first transistor and an initialization line, the fifth transistor transmitting an initialization voltage from the initialization line to the first transistor,
wherein a semiconductor pattern of the fifth transistor is disposed under the semiconductor pattern of the first transistor.

5. The display device of claim 4 , further comprising:
a sixth transistor electrically connected to a second source or drain electrode of the first transistor and an anode electrode of the organic light emitting diode, the sixth transistor transmitting the driving current from the first transistor to the organic light emitting diode,
wherein a semiconductor pattern of the sixth transistor is disposed over the semiconductor pattern of the first transistor.

6. The display device of claim 1 , wherein the semiconductor pattern of the first transistor, the semiconductor pattern of the second transistor, and the semiconductor pattern of the third transistor include a same material.

7. The display device of claim 6 , wherein the semiconductor pattern of the first transistor, the semiconductor pattern of the second transistor, and the semiconductor pattern of the third transistor constitute a PMOS transistor including polycrystalline silicon.

8. The display device of claim 1 , further comprising a capacitor including:
a first electrode electrically connected to a gate electrode of the first transistor; and
a second electrode electrically connected to the first power voltage line,
wherein the capacitor is disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor.

9. The display device of claim 1 , wherein
the lower transistor insulating film includes a first interlayer insulating film disposed over the semiconductor pattern of the second transistor, and
an upper surface of the first interlayer insulating film is substantially flat.

10. The display device of claim 9 , wherein
the upper transistor insulating film includes a second interlayer insulating film disposed over the semiconductor pattern of the first transistor, and
an upper surface of the second interlayer insulating film is substantially flat.

11. The display device of claim 1 , further comprising a first contact pattern disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the second transistor,
wherein the semiconductor pattern of the first transistor and the semiconductor pattern of the second transistor are electrically connected through the first contact pattern.

12. The display device of claim 11 , further comprising a second contact pattern disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor,
wherein the semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor are electrically connected through the second contact pattern.

13. A display device comprising:
a first transistor, a second transistor, and a third transistor that are disposed on different layers, respectively;
a capacitor;
a first semiconductor layer disposed over a substrate and including a semiconductor pattern of the first transistor;
a first gate insulating film disposed over the first semiconductor layer;
a first conductive layer disposed over the first gate insulating film and including a gate electrode of the first transistor;
a first interlayer insulating film disposed over the first conductive layer;
a second semiconductor layer disposed over the first interlayer insulating film and including a semiconductor pattern of the second transistor;
a second gate insulating film disposed over the second semiconductor layer;
a second conductive layer disposed over the second gate insulating film and including:
a gate electrode of the second transistor; and
a first electrode of the capacitor electrically connected to the gate electrode of the second transistor;

a second interlayer insulating film disposed over the second conductive layer;
a third conductive layer including a second electrode of the capacitor disposed over the second interlayer insulating film;
a third interlayer insulating film disposed over the third conductive layer;
a third semiconductor layer disposed over the third interlayer insulating film and including a semiconductor pattern of the third transistor;
a third gate insulating film disposed over the third semiconductor layer; and
a fourth conductive layer disposed over the third gate insulating film and including a gate electrode of the third transistor.

14. The display device of claim 13 , wherein
the second semiconductor layer is disposed on an upper surface of the first interlayer insulating film, and
the upper surface of the first interlayer insulating film is substantially flat.

15. The display device of claim 14 , further comprising a first contact pattern disposed in a first contact hole penetrating the first interlayer insulating film,
wherein an upper surface of the first contact pattern and the upper surface of the first interlayer insulating film are disposed on a same plane.

16. The display device of claim 14 , wherein
the third semiconductor layer is disposed on an upper surface of the third interlayer insulating film, and
the upper surface of the third interlayer insulating film is substantially flat.

17. The display device of claim 16 , furthe

Assignees

• Samsung Display Co Ltd

Inventors

• Kim June Hwan
• Kim Tae Young
• Park Jong Woo
• Im Ki Ju
• Moon Ji Ho
• Hwang Hyun Cheol

Classifications

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title