Device including programmable logic element and programmable switch

Patent metadata

Field	Value
Publication number	US-9983265-B2
Application number	US-201514612476-A
Country	US
Kind code	B2
Filing date	Feb 3, 2015
Priority date	Feb 7, 2014
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

Provided is a device capable of generating a new test pattern after the design stage with the area of a circuit that is not in use during normal operation reduced. The device includes a first circuit and a second circuit. The second circuit includes a plurality of third circuits, a plurality of fourth circuits, and a fifth circuit and has a function of generating a signal for testing operation of the first circuit and operating as part of the first circuit. The fourth circuits have a function of storing first data and second data. The fifth circuit has a function of writing the first data to the fourth circuits, writing the second data to the fourth circuits, and reading the second data from the fourth circuits. The first data is used to control the conduction between the third circuits. The second data is used for processing in the first circuit.

First claim

The invention claimed is:

1. A device comprising:
a first circuit; and
a second circuit comprising:
a plurality of programmable logic elements;
a plurality of fourth circuits; and
a fifth circuit,

wherein the second circuit is configured to generate a signal for testing operation of the first circuit and is configured to operate as part of the first circuit,
wherein each of the plurality of fourth circuits is configured to store a configuration data and is configured to store a second data,
wherein the fifth circuit is configured to write the configuration data to the plurality of fourth circuits, is configured to write the second data to the plurality of fourth circuits, and is configured to read the second data from the plurality of fourth circuits,
wherein conduction between the plurality of programmable logic elements is controlled by the configuration data,
wherein contents of logic operations in the plurality of programmable logic elements are changed by the configuration data,
wherein the first circuit performs processing using the second data,
wherein each of the plurality of fourth circuits comprises a first transistor, a second transistor, and a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,
wherein one of the source and the drain of the first transistor is electrically connected to a first terminal of the capacitor, and
wherein the first transistor comprises an oxide semiconductor film comprising a first channel formation region.

2. The device according to claim 1 ,
wherein the second circuit is configured to operate as a cache memory of the first circuit when the second circuit operates as part of the first circuit, and
wherein the second data is stored in a memory region of the cache memory.

3. The device according to claim 1 ,
wherein the configuration data is generated based on a serial data inputted to the fifth circuit, and
wherein the second data is generated based on a parallel data inputted to the fifth circuit.

4. The device according to claim 1 ,
wherein the second transistor comprises a second channel formation region comprising silicon.

5. The device according to claim 1 ,
wherein the oxide semiconductor film comprises indium, gallium, and zinc.

6. The device according to claim 5 ,
wherein a c-axis of the oxide semiconductor film is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor film.

7. The device according to claim 1 ,
wherein the fifth circuit comprises a third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the fifth circuit is configured to write the configuration data to the plurality of fourth circuits through the first transistor in a first period,
wherein the fifth circuit is configured to write the second data to the plurality of fourth circuits through the first transistor and is configured to read the second data from the plurality of fourth circuits through the second transistor in a second period, and
wherein the third transistor is turned on in the second period.

8. A device comprising:
a central processing device comprising a first memory region; and
a reconfiguration circuit configured to generate a signal for testing operation of the central processing device and is configured to operate as part of the central processing device, the reconfiguration circuit comprising:
a plurality of programmable logic elements;
a plurality of programmable switches configured to control conduction between the plurality of programmable logic elements; and
a driver circuit configured to be supplied with a serial data and output a configuration data to the plurality of programmable switches,

wherein at least parts of the plurality of programmable switches are further configured to store a second data,
wherein contents of logic operations in the plurality of programmable logic elements are changed by the configuration data,
wherein the driver circuit is further configured to be supplied with a parallel data and output the second data to the at least parts of the plurality of programmable switches,
wherein a cache memory comprises the first memory region and the at least parts of the plurality of programmable switches,
wherein each of the plurality of programmable switches comprises a first transistor, a second transistor, and a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,
wherein one of the source and the drain of the first transistor is electrically connected to a first terminal of the capacitor, and
wherein the first transistor comprises an oxide semiconductor film comprising a first channel formation region.

9. The device according to claim 8 ,
wherein the second transistor comprises a second channel formation region comprising silicon.

10. The device according to claim 8 ,
wherein the oxide semiconductor film comprises indium, gallium, and zinc.

11. The device according to claim 10 ,
wherein a c-axis of the oxide semiconductor film is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor film.

12. The device according to claim 8 ,
wherein the driver circuit comprises a third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the driver circuit is configured to write the configuration data to the plurality of programmable switches through the first transistor for a testing operation,
wherein the driver circuit is configured to write the second data to the plurality of programmable switches through the first transistor and is configured to read the second data from the plurality of programmable switches through the second transistor after the testing operation, and
wherein the third transistor is turned on after the testing operation.

Assignees

• Semiconductor Energy Lab

Inventors

• Kurokawa Yoshiyuki

Classifications

• G01R31/2856

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title

• G01R31/31919 Primary

  Storing and outputting test patterns (G01R31/31924 takes precedence; arithmetic and random test patterns generator) · CPC title

• G01R31/31813

  Test pattern generators · CPC title

• G01R31/3183

  Generation of test inputs, e.g. test vectors, patterns or sequences · CPC title

• G01R31/3187 Primary

  Built-in tests · CPC title