Method for interconnecting stacked semiconductor devices

US9627358B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9627358-B2
Application numberUS-201314368774-A
CountryUS
Kind codeB2
Filing dateSep 27, 2013
Priority dateSep 27, 2013
Publication dateApr 18, 2017
Grant dateApr 18, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for making a stacked semiconductor device comprising: molding rims on a first die and a second die, the rims extending laterally away from the first and second dice, each of the rims including upper and lower rim faces, and the first and second dice are between the respective upper and lower rim faces; stacking the second die over the first die, stacking the second die over the first die includes: engaging an upper rim face of the first die with a lower rim face of the second die, and adhering the upper rim face of the first die to the lower rim face of the second die; and drilling one or more vias through the rims after stacking, the one or more vias extending between the first and second dice. 2. The method of claim 1 further comprising filling the one or more vias with a conductive material to electrically interconnect the first and second dice. 3. The method of claim 1 , wherein molding rims includes forming a dielectric portion over the first die and the second die, the rims formed with the dielectric portion. 4. The method of claim 3 , wherein forming the dielectric portion includes molding resin around the first die and the second die, the rims formed with the resin. 5. The method of claim 1 comprising: forming a first reconstituted dice panel including a first plurality of dice molded in a panel frame, the first plurality of dice including the first die, and forming a second reconstituted dice panel including a second plurality of dice molded in another panel frame, the second plurality of dice including the second die; and molding rims includes surrounding a periphery of the dice in the first and second reconstituted dice panels with a dielectric material. 6. The method of claim 5 comprising sorting the dice in the first plurality of dice and second plurality of dice to ensure only operational dice are used to form the first and second reconstituted dice panels. 7. The method of claim 6 comprising separating individual stacks of first and second adhered dice from the first and second reconstituted dice panels. 8. The method of claim 1 , wherein drilling the one or more vias consists of one or more of laser drilling, mechanical drilling or chemical etching. 9. The method of claim 1 , wherein drilling the one or more vias is continuous through the first and second dice. 10. The method of claim 1 comprising forming one or more redistribution layers of conductive traces over one or more of the first or second dice or the rims, the one or more vias in communication with the conductive traces at the rims. 11. The method of claim 1 , wherein stacking the first die over the second die includes staggering the second die relative to the first die to expose at least one bond pad of the second die. 12. The method of claim 11 , wherein drilling the one or more vias includes drilling at least one via through the rim of the first die, the at least one via extending to the at least one bond pad of the second die. 13. A method for making a stacked semiconductor device comprising: sorting dice into a plurality of operational dice, the plurality of operational dice tested for operability; forming at least a first reconstituted dice panel including: arranging the sorted plurality of operational dice within a panel frame, and molding a resin around the plurality of operational dice within the panel frame to form the first reconstituted dice panel, rims formed with the resin extend laterally from each of the plurality operational dice, and each of the rims includes upper and lower rim faces; repeating arranging and molding to form a second reconstituted dice panel, rims extend laterally away from each die of the plurality of operational dice of the second reconstituted dice panel; coupling the first reconstituted dice panel to the second reconstituted dice panel including engaging upper rim faces of the first reconstituted dice panel with lower rim faces of the second reconstituted dice panel; and drilling one or more vias in the coupled first and second reconstituted dice panels, the one or more vias within the rims of the plurality of operational dice and the one or more vias extend between the first and second reconstituted dice panels. 14. The method of claim 13 , wherein coupling the first reconstituted dice panel to the second reconstituted dice panel includes aligning the pluralities of operational dice of each of the first and second reconstituted dice panels. 15. The method of claim 13 comprising separating the first and second reconstituted dice panels into a plurality of multi-layered packages, each of the multi-layered packages including: at least two dice of the plurality of operational dice of the first and second reconstituted dice panels, and at least one via of the one or more vias. 16. The method of claim 13 , wherein drilling one or more vias in the coupled first and second reconstituted dice panels includes drilling one or more vias through the rims of the plurality of operational dice. 17. The method of claim 13 comprising filling the one or more vias with a conductive material to electrically couple the first and second reconstituted dice panels. 18. The method of claim 13 , wherein forming at least the first reconstituted dice panel includes forming one or more redistribution layers of conductive traces over the plurality of operational dice and the respective rims, the one or more vias in communication with the conductive traces at the rims. 19. The method of claim 13 , wherein arranging the sorted plurality of operational dice within the panel frame includes arranging the sorted plurality of operational dice into one or more staggered stacks of dice within the panel frame, each of the one or more staggered stacks of dice including two or more dice and at least one of the two or more dice is staggered relative to an adjacent die. 20. The method of claim 19 , wherein molding the resin around the plurality of operation dice includes molding the resin around each of the one or more staggered stacks of dice.

Assignees

Inventors

Classifications

  • Packaging processes not covered by the other groups of this subclass · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between stacked chips · CPC title

  • between stacked chips · CPC title

  • characterised by the relative positions of pads or connectors relative to package parts · CPC title

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Frequently asked questions

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What does patent US9627358B2 cover?
A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 18 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).