Power semiconductor package with highly reliable chip topside

Patent metadata

Field	Value
Publication number	US-11538734-B2
Application number	US-201917046620-A
Country	US
Kind code	B2
Filing date	Apr 8, 2019
Priority date	Apr 11, 2018
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A power semiconductor module includes a substrate with a metallization layer and a power semiconductor chip bonded to the metallization layer of the substrate. A metallic plate has a first surface bonded to a surface of the power semiconductor chip opposite to the substrate. The metallic plate has a central part and a border that are both bonded to the power semiconductor chip. The border of the metallic plate is structured in such a way that the metallic plate has less metal material per volume at the border as compared to the central part of the metallic plate. Metallic interconnection elements are bonded to a second surface of the metallic plate at the central part.

First claim

The invention claimed is:

1. A power semiconductor module, comprising:
a substrate with a metallization layer;
a power semiconductor chip bonded to the metallization layer of the substrate;
a metallic plate with a first surface bonded to a surface of the power semiconductor chip opposite to the substrate, the metallic plate having a central part and a border that are both bonded to the power semiconductor chip, wherein the border of the metallic plate is structured in such a way that the metallic plate has less metal material per volume at the border as compared to the central part of the metallic plate; and
a plurality of metallic interconnection elements bonded to a second surface of the metallic plate at the central part.

2. The power semiconductor module of claim 1 , wherein the first surface of the metallic plate covers more than 50% of an electrode of the power semiconductor chip.

3. The power semiconductor module of claim 1 , wherein the border of the metallic plate is thinner than the central part of the metallic plate.

4. The power semiconductor module of claim 1 , wherein the border has depressions in the second surface or has holes in the second surface.

5. The power semiconductor module of claim 4 , wherein the central part of the metallic plate is flat.

6. The power semiconductor module of claim 4 , wherein the border has through holes.

7. The power semiconductor module of claim 1 , wherein the border of the metallic plate has a thickness of less than 100 μm.

8. The power semiconductor module of claim 1 , wherein the central part of the metallic plate has a thickness of more than 30 μm.

9. The power semiconductor module of claim 1 , wherein the central part of the metallic plate is flat.

10. The power semiconductor module of claim 1 , wherein the metallic interconnection elements comprise bond wires are bonded to the central part or metallic bands.

11. The power semiconductor module of claim 1 , wherein the metallic plate is made of copper.

12. A power semiconductor module, comprising:
a substrate with a metallization layer;
a power semiconductor chip bonded to the metallization layer of the substrate;
a metallic plate bonded having a central part and a border that are both bonded to a surface of the power semiconductor chip opposite to the substrate, wherein the central part of the metallic plate is structured differently than the border of the metallic plate so that thermal stresses at the border are lower during operation of the power semiconductor module and so that the central part of the metallic plate has a lower resistivity than the border of the metallic plate; and
a plurality of metallic interconnection elements bonded to a second surface of the metallic plate at the central part.

13. The power semiconductor module of claim 12 , wherein the border of the metallic plate is thinner than the central part of the metallic plate.

14. The power semiconductor module of claim 12 , wherein the border has depressions or holes and wherein the central part of the metallic plate is flat.

15. A method of manufacturing a power semiconductor module, the method comprising:
bonding a power semiconductor chip to a metallization layer of a substrate;
structuring a border of a metallic plate, such that the metallic plate has less metal material per volume at the border as compared to a central part of the metallic plate;
bonding a first surface of the metallic plate to the power semiconductor chip opposite to the substrate, wherein the central part and the border are both bonded to the power semiconductor chip; and
attaching a plurality of interconnection elements to a second surface of the metallic plate at the central part of the metallic plate.

16. The method of claim 15 , wherein structuring the border of the metallic plate comprises performing electrochemical etching.

17. The method of claim 15 , wherein structuring the border of the metallic plate comprises stamping.

18. The method of claim 15 , wherein bonding the metallic plate to the power semiconductor chip comprises sintering the metallic plate to the power semiconductor chip.

19. The method of claim 15 , attaching the interconnection elements comprises ultrasonic welding the interconnection elements to the central part.

20. The method of claim 15 , wherein attaching the interconnection elements comprises laser welding the interconnection elements to the central part.

Assignees

• Hitachi Energy Switzerland Ag

Inventors

• Mohn Fabian
• Sokolov Alexey
• Liu Chunlei

Classifications

• H10W70/02

  of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W72/534

  being rectangular · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title