Semiconductor package

Patent metadata

Field	Value
Publication number	US-9601453-B2
Application number	US-201314104805-A
Country	US
Kind code	B2
Filing date	Dec 12, 2013
Priority date	Jun 28, 2013
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die.

First claim

What is claimed is:

1. A semiconductor package comprising:
a monolithic type first die comprising a driver circuit and a low-side output power device connected to the driver circuit;
a second die disposed above the first die, the second die comprising a high-side output power device;
a first connection unit connecting a top of the first die and a bottom of the second die; and
a second connection unit disposed on the second die.

2. The semiconductor package of claim 1 , wherein the low-side output power device comprises a bottom-source lateral double diffused metal oxide semiconductor (LDMOS).

3. The semiconductor package of claim 1 , wherein the first die comprises a power electrode provided on a bottom surface thereof.

4. The semiconductor package of claim 3 , wherein the power electrode is electrically connected to a power ground.

5. The semiconductor package of claim 4 , wherein a portion of the second connection unit connects an electrode of the high-side output power device to an input voltage.

6. The semiconductor package of claim 1 , wherein the high-side output power device comprises a bottom-source LDMOS that is unflipped.

7. The semiconductor package of claim 1 , wherein the high-side output power device comprises a VDMOS.

8. The semiconductor package of claim 1 , wherein the high-side output power device comprises a bottom-drain LDMOS.

9. The semiconductor package of claim 1 , wherein the second die comprises electrodes formed on both a top surface and a bottom surface thereof.

10. The semiconductor package of claim 1 , wherein the high-side output power device comprises a bottom-source LDMOS that is a flip chip.

11. The semiconductor package of claim 2 , wherein a source region of the bottom-source LDMOS is connected to a power electrode provided on a bottom surface of the first die, and a source current is grounded.

12. The semiconductor package of claim 11 , further comprising a high concentration doping region on the power electrode,
wherein the high concentration doping region and a source region of the bottom-source LDMOS are connected using a trench.

13. The semiconductor package of claim 9 , wherein the electrode formed on the bottom surface of the second die is a power electrode configured to be grounded by a lead frame disposed between the first die and the second die.

14. A mobile communication terminal comprising a semiconductor package of claim 1 .

15. The semiconductor package of claim 1 , wherein the first die comprises a substrate and a source region of the low-side output power device.

16. The semiconductor package of claim 15 , wherein the source region of the low-side output power device is electrically connected with a bottom surface of the substrate through a trench structure, wherein the trench structure is filled with poly-Si or a conductive metal.

17. The semiconductor package of claim 2 , further comprising a backmetal disposed on a bottom surface of the first die, wherein the backmetal is electrically connected to a source region of the LDMOS device.

18. The semiconductor package of claim 17 , wherein the backmetal comprises a material selected from the group consisting of Ti/Ni/Ag, Ti/Ni/Au, Ti/TiN/Al and Ti/Ni/Cu.

19. A semiconductor package comprising:
a monolithic type first die comprising a driver circuit and a low-side output power device connected to the driver circuit;
a second die disposed above the first die, the second die comprising a high-side output power device; and
a connection unit connecting an electrode on a top surface of the second die to an input voltage.

20. The semiconductor package of claim 19 , wherein at least a portion of a bottom surface of the second die is electrically connected to at least a portion of a top surface of the first die.

21. The semiconductor package of claim 19 , wherein a source region of the low-side output power device is electrically connected with a backmetal provided on a bottom surface of the first die.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Hebert Francois

Classifications

• H10W72/07654

  changes in dispositions · CPC title

• H10W72/647

  Dispositions of multiple strap connectors · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/637

  Multiple strap connectors having different shapes · CPC title

• H10W72/646

  the connected ends being on auxiliary connecting means on bond pads, e.g. on a bump connector · CPC title