Auto-referenced memory cell read techniques

Patent metadata

Field	Value
Publication number	US-10431301-B2
Application number	US-201715853364-A
Country	US
Kind code	B2
Filing date	Dec 22, 2017
Priority date	Dec 22, 2017
Publication date	Oct 1, 2019
Grant date	Oct 1, 2019

Abstract

Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

First claim

What is claimed is:

1. A method, comprising:
initializing a counter in a controller coupled with a memory array;
activating at least a portion of a first group of memory cells of the memory array by applying a read voltage to the memory array;
determining that a set of memory cells has been activated based at least in part on applying the read voltage;
updating the counter to a first value based at least in part on determining that the set of memory cells has been activated;
comparing the first value of the updated counter to a threshold stored at the controller; and
reading one or more memory cells of the memory array based at least in part on the comparison.

2. The method of claim 1 , wherein the comparing further comprises:
determining that the first value satisfies the threshold stored at the controller; and
stopping application of the read voltage to the memory array based at least in part on the determination that the first value satisfies the threshold, wherein the one or more memory cells are read after application of the read voltage has stopped.

3. The method of claim 1 , wherein the comparing further comprises:
determining that the first value does not satisfy the threshold stored at the controller;
maintaining application of the read voltage to the memory array based at least in part on the determination that the first value does not satisfy the threshold;
determining that a second set of memory cells has been activated based at least in part on maintaining application of the read voltage; and
updating the counter to a second value based at least in part on determining that the second set of memory cells has been activated, wherein the one or more memory cells are read based at least in part on updating the counter to the second value.

4. The method of claim 1 , further comprising:
determining that the set of memory cells that has been activated corresponds to a first logic state.

5. The method of claim 4 , wherein the first logic state corresponds to a first set of threshold voltages that is less than a second set of threshold voltages associated with a second logic state.

6. The method of claim 1 , wherein the first group of memory cells are configured with a predetermined number of memory cells having a first logic state.

7. The method of claim 1 , wherein the first group of memory cells are configured with a fixed number of memory cells independent of a total number of memory cells in the first group.

8. The method of claim 1 , wherein a first half of the first group of memory cells corresponds to a first logic state and a second half of the first group of memory cells corresponds to a second logic state.

9. The method of claim 1 , wherein each memory cell of the set of memory cells corresponds to a first logic state.

10. The method of claim 1 , wherein the set of memory cells is half of the first group of memory cells.

11. The method of claim 6 , wherein the threshold is equal to the predetermined number of memory cells having the first logic state.

12. The method of claim 1 , wherein the threshold is read from a second group of memory cells of the memory array.

13. The method of claim 1 , wherein the read voltage comprises a plurality of constant voltages each having a different value over a duration.

Assignees

• Micron Technology Inc

Inventors

• Mirichigni Graziano
• Amato Paolo
• Pio Federico
• Orlando Alessandro
• Sforzin Marco

Classifications

• G11C11/5678 Primary

  using amorphous/crystalline phase transition storage elements · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C2213/76

  Array using an access device for each cell which being not a transistor and not a diode · CPC title

• G11C2213/71

  Three dimensional array · CPC title