Auto-referenced memory cell read techniques

Patent metadata

Field	Value
Publication number	US-10600480-B2
Application number	US-201916536120-A
Country	US
Kind code	B2
Filing date	Aug 8, 2019
Priority date	Dec 22, 2017
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

First claim

What is claimed is:

1. A method, comprising:
initializing a first counter and a second counter in a controller coupled with a memory array that comprises a first portion of memory cells and a second portion of memory cells;
activating a first subset of the first portion of memory cells by applying a first read voltage to the memory array and a second subset of the second portion of memory cells by applying a second read voltage to the memory array;
updating the first counter to a first value based at least in part on activating the first subset of the first portion of memory cells and the second counter to a second value based at least in part on activating the second subset of the second portion of memory cells; and
reading one or more memory cells of the first portion of memory cells based at least in part on updating the first counter and the second counter.

2. The method of claim 1 , further comprising:
comparing the second value of the updated second counter to a threshold, wherein reading one or more memory cells of the first portion of memory cells is based at least in part on comparing the second value of the updated second counter to the threshold.

3. The method of claim 2 , wherein the comparing further comprises:
determining that the second value satisfies the threshold;
stopping application of the second read voltage based at least in part on the determination that the second value satisfies the threshold; and
identifying, from the second portion of memory cells, a total number of memory cells of the first portion having a first logic state based at least in part on the determination that the second value satisfies the threshold.

4. The method of claim 3 , further comprising:
determining that the first value corresponds to the identified total number; and
stopping application of the first read voltage based at least in part on the determination that the first value corresponds to the identified total number, wherein the one or more memory cells of the first portion of memory cells are read after application of the first read voltage has stopped.

5. The method of claim 3 , further comprising:
determining that the first value does not correspond to the identified total number; and
maintaining application of the first read voltage based at least in part on the determination that the first value does not correspond to the identified total number.

6. The method of claim 3 , further comprising:
setting a flag in the controller based at least in part on identifying the total number of memory cells of the first portion having the first logic state.

7. The method of claim 2 , wherein the comparing further comprises:
determining that the second value does not satisfy the threshold; and
maintaining application of the second read voltage based at least in part on the determination that the second value does not satisfy the threshold.

8. The method of claim 1 , wherein the first read voltage and the second read voltage are a same single read voltage.

9. The method of claim 1 , wherein the first read voltage is configured to have a time offset with respect to the second read voltage.

10. The method of claim 1 , wherein the first read voltage is configured to have a different rate of voltage change with respect to the second read voltage.

11. An apparatus, comprising:
a memory array that comprises a first portion of memory cells and a second portion of memory cells; and
a controller coupled with the memory array and operable to cause the apparatus to:
initialize a first counter and a second counter;
activate a first subset of the first portion of memory cells by applying a first read voltage to the memory array and a second subset of the second portion of memory cells by applying a second read voltage to the memory array;
update the first counter to a first value based at least in part on activating the first subset of the first portion of memory cells and the second counter to a second value based at least in part on activating the second subset of the second portion of memory cells; and
read one or more memory cells of the first portion of memory cells based at least in part on updating the first counter and the second counter.

12. The apparatus of claim 11 , wherein the controller is further operable to cause the apparatus to:
compare the second value of the updated second counter to a threshold, wherein reading one or more memory cells of the first portion of memory cells is based at least in part on comparing the second value of the updated second counter to the threshold.

13. The apparatus of claim 12 , wherein the controller is further operable to cause the apparatus to:
determine that the second value satisfies the threshold;
stop application of the second read voltage based at least in part on the determination that the second value satisfies the threshold; and
identify, from the second portion of memory cells, a total number of memory cells of the first portion having a first logic state based at least in part on the determination that the second value satisfies the threshold, wherein the comparing is based at least in part on the identifying.

14. The apparatus of claim 13 , wherein the controller is further operable to cause the apparatus to:
determine that the first value corresponds to the identified total number; and
stop application of the first read voltage based at least in part on the determination that the first value corresponds to the identified total number, wherein the one or more memory cells of the first portion of memory cells are read after application of the first read voltage has stopped.

15. The apparatus of claim 13 , wherein the controller is further operable to cause the apparatus to:
determine that the first value does not correspond to the identified total number; and
maintain application of the first read voltage based at least in part on the determination that the first value does not correspond to the identified total number.

16. The apparatus of claim 13 , wherein the controller is further operable to cause the apparatus to:
set a flag in the controller based at least in part on identifying the total number of memory cells of the first portion having the first logic state.

17. The apparatus of claim 11 , wherein the first read voltage is configured to have a time offset with respect to the second read voltage.

18. An apparatus, comprising:
a memory array that comprises a first portion of memory cells and a second portion of memory cells;
a biasing component coupled with the memory array and operable to activate a first subset of the first portion of memory cells by applying a first read voltage to the memory array and a second subset of the second portion of memory cells by applying a second read voltage to the memory array;
a controller coupled with the memory array and operable to cause the apparatus to:
initialize a first counter and a second counter in the controller; and
update the first counter to a first value based at least in part on the biasing component activating the first subset of the first portion of memory cells and the second counter to a second value based at least in part on activating the second subset of the second portion of memory cells; and

a sense component operable to read one or more memory cells of the first portion of memory cells based at least in part on the first counter and the second counter being updated.

19. The apparatus of claim 18 , wherein the controller is further operable to:
compare the second value o

Assignees

• Micron Technology Inc

Inventors

• Mirichigni Graziano
• Amato Paolo
• Pio Federico
• Orlando Alessandro
• Sforzin Marco

Classifications

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C13/003

  Cell access · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C11/5678 Primary

  using amorphous/crystalline phase transition storage elements · CPC title