Semiconductor device and semiconductor package including the semiconductor device

Patent metadata

Field	Value
Publication number	US-11538506-B2
Application number	US-202117356080-A
Country	US
Kind code	B2
Filing date	Jun 23, 2021
Priority date	Jul 21, 2020
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A semiconductor device includes a cell area in which a plurality of memory cells are arranged in an array structure, and a peripheral area in which circuits configured to drive the memory cells are arranged, the peripheral area being next to the cell area. The cell area is divided into a plurality of banks, and the plurality of banks comprise first banks having a base size and second banks having a size of 1/(2*n) (wherein n is an integer greater than or equal to 1) of the base size. The plurality of banks are arranged in a first direction and a second direction perpendicular to the first direction, and the semiconductor device has a shape of a rectangular chip which is elongated in the second direction.

First claim

What is claimed is:

1. A semiconductor device comprising:
a cell area in which a plurality of memory cells are arranged in an array structure;
at least two peripheral areas in which circuits configured to drive the memory cells are arranged, the at least two peripheral areas being arranged next to the cell area,
wherein:
the cell area is divided into a plurality of banks,
the plurality of banks comprise first banks having a first size and second banks having a size of 1/(2*n) (wherein n is an integer greater than or equal to 1) of the first size, and
the at least two peripheral areas each extend in a first direction and are directly adjacent to the plurality of banks; and
chip pads arranged in an “L” shape adjacent to an outer edge of a chip,
wherein the semiconductor device has a shape of a rectangular chip which is elongated in a second direction perpendicular to the first direction.

2. The semiconductor device of claim 1 , wherein:
each of the second banks has a size of ½ of the first size,
the cell area comprises fifteen first banks and two second banks,
five first banks are arranged in each of three sequentially-arranged rows, each row extending in the first direction, and three first banks are arranged in each of five columns, each column extending in the second direction, and
the two second banks are each arranged between two of the first banks in the first direction, wherein one of the two second banks is in a first row of the three sequentially-arranged rows, and another of the two second banks is in a second row of the three sequentially-arranged rows.

3. The semiconductor device of claim 2 , wherein:
the at least two peripheral areas comprise a first peripheral area and a second peripheral area,
the first peripheral area is between the first row and the second row,
the second peripheral area is outside the first banks in the second direction, and
the plurality of banks in the second row and a plurality of banks in a third row of the three sequentially-arranged rows are between the first peripheral area and the second peripheral area.

4. The semiconductor device of claim 3 , further comprising an additional peripheral area extending in the second direction and arranged between a set of the second banks and a set of the first banks in the first direction.

5. The semiconductor device of claim 2 , wherein:
the two second banks are arranged to be aligned with each other in the second direction, and
an additional bank area is outside the two second banks or between the two second banks in the second direction.

6. The semiconductor device of claim 1 , wherein:
the chip pads comprise first pads for a package operation and second pads for testing,
the first pads are arranged on a short side of the rectangular chip, and the second pads are arranged on a long side of the rectangular chip.

7. The semiconductor device of claim 6 , wherein some of the first pads are arranged on the long side of the rectangular chip.

8. The semiconductor device of claim 1 , wherein:
the rectangular chip has a size of less than or equal to 5.7 mm in the first direction and a size of less than or equal to 10.92 mm in the second direction, and
the semiconductor device has a memory capacity of 16 gigabits (Gb).

9. A semiconductor device comprising:
a cell area in which a plurality of memory cells are arranged in an array structure; and
a peripheral area in which circuits configured to drive the memory cells are arranged, the peripheral area being next to the cell area,
wherein:
the cell area is divided into a plurality of banks,
the plurality of banks comprise first banks having a base size and second banks having a size of 1/(2*n) (wherein n is an integer greater than or equal to 1) of the base size, the plurality of banks being arranged in a first direction and a second direction perpendicular to the first direction, and
the semiconductor device has a shape of a rectangular chip which is elongated in the second direction.

10. The semiconductor device of claim 9 , wherein:
each of the second banks has a size of ½ of the base size,
the cell area comprises fifteen first banks and two second banks,
five first banks are arranged in each of three sequentially-arranged rows, each row extending in the first direction, and three first banks are arranged in each of five columns, each column extending in the second direction, and
the two second banks are each arranged between two of the first banks in the first direction, wherein one of the two second banks is in a first row of the three sequentially-arranged rows, and another of the two second banks is in a second row of the three sequentially-arranged rows.

11. The semiconductor device of claim 10 , wherein:
the peripheral area comprises a first peripheral area and a second peripheral area,
each of the first peripheral area and the second peripheral area extends in the first direction,
the first peripheral area is between the first row and the second row, and
the second peripheral area is at an outer portion of the rectangular chip in the second direction.

12. The semiconductor device of claim 9 , further comprising chip pads arranged in an “L” shape at an outer portion of the rectangular chip.

13. The semiconductor device of claim 12 , wherein:
the chip pads comprise first pads for a package operation and second pads for testing,
the first pads are arranged on a short side or the short side and a long side of the rectangular chip, and the second pads are arranged on the long side of the rectangular chip.

14. A semiconductor package comprising:
a package substrate;
a first stack structure in which a plurality of chips are stacked, the first stack structure being mounted on the package substrate;
a second stacked structure in which a same number of chips as that of the first stack structure are stacked, the second stacked structure being mounted on the package substrate and arranged to be horizontally adjacent to the first stacked structure; and
a sealing material sealing the first stacked structure and the second stacked structure on the package substrate,
wherein each of the plurality of chips comprises a cell area in which a plurality of memory cells are arranged in an array structure and a peripheral area in which circuits configured to drive the plurality of memory cells are arranged, the peripheral area being next to the cell area,
wherein the cell area is divided into a plurality of banks,
the plurality of banks comprise first banks having a base size and second banks having a size of 1/(2*n) (wherein n is an integer greater than or equal to 1) of the base size, the plurality of banks being arranged in a first direction and a second direction perpendicular to the first direction, and
each chip of the plurality of chips has a shape of a rectangular chip which is elongated in the second direction.

15. The semiconductor package of claim 14 , wherein:
the package substrate is 12.4 mm or less in the first direction and 14 mm or less in the second direction, and
each chip of the plurality of chips has a capacity of 16 Gb.

16. The semiconductor package of claim 14 , wherein:
each of the second banks has a size of ½ of the base size,
the cell area comprises fifteen first banks and two second banks,
five first banks are arranged in each of three sequentially-arranged rows, each row extending in the first direction, and three first banks are arranged in each of five columns, each column extending in the second direction, and
the two second banks are each arranged between two of the first banks in the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyungjin
• Kim Yongjun
• Kim Yonghun
• Ahn Minsu
• Oh Reum
• Choi Jinyong

Classifications

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C5/06 Primary

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title