Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10957368-B2
Application number	US-201916546064-A
Country	US
Kind code	B2
Filing date	Aug 20, 2019
Priority date	Jan 13, 2016
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

A semiconductor memory device according to an embodiment includes: a row decoder and a memory cell array including a first block. The first block includes: a first region, a second region adjacent to the first region in the first direction, and a third region configured to connect the first region and the second region. The memory cell array further includes: a first insulating layer buried in a first trench between the first region and the second region and in contact with the third region; a first contact plug provided in the first insulating layer and electrically connected to the row decoder; and a first interconnect configured to connect a selection gate line and the first contact plug.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a row decoder provided on a semiconductor substrate including a first surface;
a memory cell array provided above the row decoder and including a set of cell regions arranged in a matrix, the memory cell array including an interconnect connected to the row decoder and overlapping the row decoder on a plane along the first surface; and
a first connecting portion,
wherein the row decoder includes a first transistor provided outside an outer periphery of the set of the cell regions on the plane along the first surface, and
the first connecting portion is provided between the first transistor and one cell region of the set of the cell regions and includes a first contact plug configured to connect the interconnect and the row decoder.

2. The semiconductor memory device according to claim 1 , wherein the row decoder further includes a second transistor overlapping the memory cell array on the plane along the first surface, and
the semiconductor memory device further comprises a sense amplifier provided on the semiconductor substrate and overlapping the memory cell array on the plane along the first surface.

3. The semiconductor memory device according to claim 1 , wherein the set of the cell regions includes a first cell region and a second cell region which are adjacent to each other,
the first transistor is located outside an outer periphery of the first cell region on the plane along the first surface, and
the semiconductor memory device further comprises a dummy region provided outside an outer periphery of the second cell region on the plane along the first surface and including an active region and a conductor.

4. The semiconductor memory device according to claim 3 , wherein the first connecting portion is provided between the first cell region and the first transistor,
the interconnect of the first cell region is electrically connected to the first transistor via the first connecting portion, and
the semiconductor memory device further comprises a second connecting portion provided between the second cell region and the dummy region and including a second contact plug configured to connect the interconnect of the second cell region to the row decoder located immediately under the second cell region.

5. A semiconductor memory device comprising:
a semiconductor substrate having a surface extending in a first direction and a second direction crossing the first direction;
a first row decoder provided on the semiconductor substrate;
a memory cell array provided above the first row decoder in a third direction crossing the first direction and the second direction, the memory cell array including a plurality of blocks arranged along the second direction, the plurality of blocks including
a first block including
a first region extending in the first direction and the second direction and having a first width in the second direction,
a second region being provided at a one side in the first direction, extending in the first direction and the second direction, and having a second width in the second direction, and
a third region being provided between the first region and the second region in the first direction, extending in the first direction and the second direction, and having a third width in the second direction,
the third width being smaller than both the first width and the second width such that one sides of the first to third regions in the second direction are non-continuous along the first direction and the other sides of the first to third regions in the second direction are continuous along the first direction, and
a second block including
a fourth region extending in the first direction and the second direction and having a fourth width in the second direction,
a fifth region being provided at the one side in the first direction, extending in the first direction and the second direction, and having a fifth width in the second direction, and
a sixth region being provided between the fourth region and the fifth region in the first direction, extending in the first direction and the second direction, and having a sixth width in the second direction,
the sixth width being smaller than both the fourth width and the fifth width such that one sides of the fourth to sixth regions in the second direction are continuous along the first direction and the other sides of the fourth to sixth regions in the second direction are non-continuous along the first direction;

a first interconnect being connected between the first block and the first row decoder and overlapping the first row decoder when viewed in the third direction; and
a second interconnect being connected between the second block and the first row decoder and overlapping the first row decoder when viewed in the third direction,
wherein the first row decoder includes a first transistor overlapping the second region or the fifth region when viewed in the third direction.

6. The semiconductor memory device according to claim 5 , wherein
each of the first region and the second region includes a plurality of three-dimensionally-arranged memory cells;
the first row decoder further includes a second transistor overlapping the first region or the fourth region when viewed in the third direction, and
the semiconductor memory device further comprises a sense amplifier being provided on the semiconductor substrate and overlapping the memory cell array when viewed in the third direction.

7. The semiconductor memory device according to claim 6 , further comprising:
a first connecting portion provided between the first transistor and the first region or the fourth region and including a first contact plug configured to connect the first interconnect and the first row decoder.

8. The semiconductor memory device according to claim 7 , wherein
the semiconductor memory device further comprises a dummy region provided outside an outer periphery of the first block and outside an outer periphery of the second block when viewed in the third direction and including an active region and a conductor.

9. The semiconductor memory device according to claim 8 , wherein
the first connecting portion is provided between the first region and the first transistor,
the first interconnect of the first region is electrically connected to the first transistor via the first connecting portion, and
the semiconductor memory device further comprises a second connecting portion provided between the second region and the dummy region and including a second contact plug configured to connect the first interconnect of the second region to the first row decoder.

10. The semiconductor memory device according to claim 5 , wherein
the memory cell array includes at least one source line provided above the semiconductor substrate, and a word line provided for each of the plurality of the blocks above the source line,
the semiconductor memory device further comprises:
a wall surrounding the memory cell array when viewed in the third direction, including a plurality of conductive layers arranged in the third direction from a layer of the at least one source line to a layer of the word line, and including a recess at an inner surface extending from an upper surface to a lower surface along the third direction; and
an insulating layer provided from a position of the upper surface of the wall to a position of the lower surface in the third direction and being in contact with the inner surface of the wall in the recess.

11. The semiconductor memory device according to claim 10 , wherein
the recess is provided in a region of the inner surface of the wall, facing the one side of th

Assignees

• Toshiba Memory Corp

Inventors

• Futatsuyama Takuya

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title