Semiconductor package with PoP structure and refresh control method thereof

Patent metadata

Field	Value
Publication number	US-9570147-B2
Application number	US-201514964532-A
Country	US
Kind code	B2
Filing date	Dec 9, 2015
Priority date	Jan 9, 2015
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A refresh control method of a semiconductor package, comprising: providing a semiconductor package including a first semiconductor chip and a second semiconductor chip; monitoring a temperature of each of a plurality of sensing areas of the first semiconductor chip when the first semiconductor chip operates; identifying at least one memory bank of the second semiconductor chip corresponding to an area having a lower temperature among the sensing areas; controlling the second semiconductor chip to transfer data to the identified memory bank from another memory bank of the second semiconductor chip; and controlling a refresh operation of the second semiconductor chip such that a period of a refresh operation on the identified memory bank is greater than that of a period of a refresh operation on the other memory bank.

First claim

What is claimed is:

1. A refresh control method of a semiconductor package, comprising:
providing a semiconductor package including a first semiconductor chip and a second semiconductor chip;
monitoring a temperature of each of a plurality of sensing areas of the first semiconductor chip when the first semiconductor chip operates;
identifying at least one memory bank of the second semiconductor chip in a position within the second semiconductor chip corresponding to a sensing area having a lower temperature among the sensing areas;
controlling the second semiconductor chip to transfer data to the identified memory bank from another memory bank of the second semiconductor chip; and
controlling a refresh operation of the second semiconductor chip such that a period of a refresh operation on the identified memory bank is greater than that of a period of a refresh operation on the other memory bank.

2. The refresh control method as set forth in claim 1 , wherein monitoring the temperature of each of the sensing areas of the first semiconductor chip comprises:
monitoring a plurality of thermal sensors disposed between the first semiconductor chip and a substrate on which the first semiconductor chip is mounted.

3. The refresh control method as set forth in claim 1 , wherein monitoring the temperature of each of the sensing areas of the first semiconductor chip comprises:
monitoring a number of a thermal sensors disposed between the first semiconductor chip and a substrate on which the second semiconductor chip is mounted.

4. The refresh control method as set forth in claim 1 , wherein the second semiconductor chip is a DRAM chip and the first semiconductor chip is a logic chip.

5. The refresh control method as set forth in claim 1 , wherein the second semiconductor chip is one of multiple DRAM chips stacked in at least two layers and the first semiconductor chip is an application processor.

6. The refresh control method as set forth in claim 1 , wherein the second semiconductor chip is a DDR4 DRAM chip having a multi-chip package (MCP) structure using a silicon-through via (TSV) and the first semiconductor chip is an application processor implemented with a system-on-chip.

7. The refresh control method as set forth in claim 1 , further comprising:
controlling the second semiconductor chip to not perform a refresh operation on the other memory bank when the other memory bank is empty.

8. The refresh control method as set forth in claim 1 , further comprising:
managing an address mapping table to indicate a data transfer path when the second semiconductor chip is controlled to transfer data stored in the other memory bank to the identified memory bank.

9. The refresh control method as set forth in claim 8 , further comprising:
storing and managing the address mapping table in a nonvolatile storage area in the first semiconductor chip.

10. The refresh control method as set forth in claim 1 , wherein the monitoring of the temperature in each of the sensing areas of the first semiconductor chip is performed in each of a plurality of predetermined monitoring periods.

11. The refresh control method as set forth in claim 1 , wherein
providing the semiconductor package including the first semiconductor chip and the second semiconductor chip comprises providing the semiconductor package including the first semiconductor chip and the second semiconductor chip in separate packages of the semiconductor package.

12. The refresh control method as set forth in claim 1 , wherein the lower temperature is a lowest temperature of all of the sensing areas.

13. A refresh control method of a semiconductor package, the refresh control method comprising:
providing a semiconductor package including a first semiconductor chip and including a second semiconductor chip as a memory chip;
monitoring a temperature of each of a plurality of sensing areas of the second semiconductor chip when the first semiconductor chip operates as a system-on-chip;
identifying at least one memory bank of the second semiconductor chip corresponding to an area having a lower temperature among the sensing areas;
controlling the second semiconductor chip to transfer data stored in a memory bank other than the identified at least one memory bank to the identified at least one memory bank; and
controlling a refresh operation of the second semiconductor chip such that a period of a refresh operation on the identified at least one memory bank is made longer than that of a refresh operation on the memory bank other than the identified at least one memory bank.

14. The refresh control method as set forth in claim 13 , wherein the first semiconductor chip is an application processor and the second semiconductor chip is a DRAM.

15. The refresh control method as set forth in claim 13 , wherein monitoring the temperature of each of the sensing areas of the second semiconductor chip comprises:
monitoring a plurality of thermal sensors disposed in a package on which the second semiconductor chip is mounted.

16. The refresh control method as set forth in claim 13 , wherein each of the sensing areas corresponds to one or more of physical positions of memory banks of the second semiconductor chip.

17. The refresh control method as set forth in claim 13 , further comprising:
controlling the second semiconductor chip to not perform a refresh operation on the memory bank other than the identified at least one memory bank when the memory bank other than the identified at least one memory bank is empty.

Assignees

• Kim Il-Joon
• Samsung Electronics Co Ltd

Inventors

• Kim Il-Joon

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title