Methods and apparatus for configuring an ultrasound device with imaging parameter values
US-2019142388-A1 · May 16, 2019 · US
US11536818B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11536818-B2 |
| Application number | US-202016910897-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 24, 2020 |
| Priority date | Jun 25, 2019 |
| Publication date | Dec 27, 2022 |
| Grant date | Dec 27, 2022 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Aspects of the technology described herein related to an ultrasound processing unit (UPU) including gray-coding circuitry configured to convert standard binary-coded digital ultrasound signals to gray-coded digital ultrasound signals and gray-decoding circuitry coupled to the gray-coding circuitry and configured to convert the gray-coded digital ultrasound signals to standard binary-coded digital ultrasound signals. The UPU may include an analog portion, a digital portion, and a data bus configured to route the gray-coded digital ultrasound signals from the analog portion to the digital portion subsequent to converting the standard binary-coded digital ultrasound signals to the gray-coded digital ultrasound signals. The analog portion may include multiple analog front-ends (AFEs), the gray-coding circuitry, and an analog-to-digital converter. The digital portion may include the gray-decoding circuitry. A data bus from one AFE may pass over another AFE.
Opening claim text (preview).
What is claimed is: 1. An ultrasound processing unit (UPU), comprising: an analog portion configured to receive analog ultrasound signals, the analog portion comprising: multiple analog front-ends (AFEs) comprising a first AFE and a second AFE, the first AFE of the multiple AFEs comprising: an analog-to-digital converter (ADC) configured to convert the analog ultrasound signals to standard binary-coded digital ultrasound signals; and gray-coding circuitry coupled to the ADC and configured to convert the standard binary-coded digital ultrasound signals from the ADC to gray-coded digital ultrasound signals; and a data bus configured to route the gray-coded digital ultrasound signals from the first AFE to the second AFE; wherein the data bus passes over the second AFE of the multiple AFEs; and a digital portion comprising gray-decoding circuitry configured to convert the gray-coded digital ultrasound signals to standard binary-coded digital ultrasound signals. 2. The ultrasound processing unit of claim 1 , wherein the digital portion comprises digital processing circuitry. 3. The ultrasound processing unit of claim 1 , further comprising multiple data buses each coupled between one of the multiple AFEs and the digital portion. 4. The ultrasound processing unit of claim 1 , wherein the analog portion and the digital portion are physically separated. 5. The ultrasound processing unit of claim 1 , wherein the analog portion further comprises a pulser, a switch, and analog processing circuitry. 6. The ultrasound processing unit of claim 1 , wherein: an ultrasound-on-chip comprises the ultrasound processing unit; and the multiple AFEs are arranged along an elevational dimension of the ultrasound-on-chip. 7. The ultrasound processing unit of claim 6 , further comprising: ultrasonic transducers physically located on top of each of the AFEs and arranged along the elevational dimension of the ultrasound-on-chip. 8. The ultrasound processing unit of claim 6 , wherein the ultrasound-on-chip comprises an array of ultrasonic transducers along an azimuthal dimension and an elevational dimension of the ultrasound-on-chip. 9. The ultrasound processing unit of claim 1 , wherein the gray-coding circuitry is configured to convert the standard binary-coded digital ultrasound signals to hybrid gray-coded digital ultrasound signals. 10. The ultrasound processing unit of claim 9 , wherein the gray-decoding circuitry is configured to convert the hybrid gray-coded digital ultrasound signals to the standard binary-coded digital ultrasound signals. 11. An ultrasound processing unit (UPU), comprising: gray-coding circuitry configured to convert standard binary-coded digital ultrasound signals to full gray-coded digital ultrasound signals, wherein: the gray-coding circuitry is configured to convert a standard binary coded value b N-1 b N-2 . . . b 1 b 0 to a gray coded value g N-1 g N-2 . . . g 1 g 0 ; the gray-coding circuitry includes an exclusive-or (XOR) gate for outputting each of g N-2 , g N-3 . . . g 1 , and g 0 , where an XOR gate for outputting a given g i takes as input b i+1 and b i ; and the gray-coding circuitry is configured to output g N-1 =b N-1 . 12. The ultrasound processing unit of claim 11 , wherein the gray-coding circuitry is configured to convert the standard binary-coded digital ultrasound signals to the full gray-coded digital ultrasound signals such that every transition from one binary code to an adjacent binary code differs by only a single bit. 13. An ultrasound processing unit (UPU), comprising: gray-coding circuitry configured to convert standard binary-coded digital ultrasound signals to full gray-coded digital ultrasound signals, wherein: the gray-decoding circuitry is configured to convert the full gray-coded digital ultrasound signals to the standard binary-coded digital ultrasound signals; the gray-decoding circuitry is configured to convert a gray coded value g N-1 g N-2 . . . g 1 g 0 to a standard binary coded value b N-1 b N-2 . . . b 1 b 0 ; the gray-decoding circuitry includes an exclusive-or (XOR) gate for outputting each of b N-2 , b N-3 . . . b 1 , and b 0 , where an XOR gate for outputting a given b i takes as input g i and b i+1 ; and the gray-decoding circuitry is configured to output b N-1 =g N-1 . 14. An ultrasound processing unit (UPU), comprising: gray-coding circuitry configured to convert standard binary-coded digital ultrasound signals to hybrid gray-coded digital ultrasound signals; wherein the gray-coding circuitry is configured to convert the standard binary-coded digital ultrasound signals to the hybrid gray-coded digital ultrasound signals such that: a transition from mid-code to an adjacent binary code uses a gray code system in that this transition differs by only a single bit; and other transitions use a standard binary code system. 15. An ultrasound processing unit (UPU), comprising: gray-coding circuitry configured to convert standard binary-coded digital ultrasound signals to hybrid gray-coded digital ultrasound signals, wherein: the gray-coding circuitry is configured to convert a standard binary coded value b N-1 b N-2 . . . b 1 b 0 to a gray coded value g N-1 g N-2 . . . g 1 g 0 ; the gray-coding circuitry includes an exclusive-or (XOR) gate for outputting each of g N-2 , g N-3 . . . g 1 , and g 0 , where an XOR gate for outputting a given g i takes as input b N-1 and b i ; and the gray-coding circuitry is configured to output g N-1 =b N-1 . 16. An ultrasound processing unit (UPU), comprising: gray-coding circuitry configured to convert standard binary-coded digital ultrasound signals to hybrid gray-coded digital ultrasound signals; and gray-decoding circuitry, wherein: the gray-coding circuitry is configured to convert the standard binary-coded digital ultrasound signals to hybrid gray-coded digital ultrasound signals; the gray-decoding circuitry is configured to convert the hybrid gray-coded digital ultrasound signals to the standard binary-coded digital ultrasound signals; the gray-decoding circuitry is configured to convert a gray coded value g N-1 g N-2 . . . g 1 g 0 to a standard binary coded value b N-1 b N-2 . . . b 1 b 0 ; the gray-decoding circuitry includes an exclusive-or (XOR) gate for outputting each of b N-2 , b N-3 . . . b 1 , and b 0 , where an XOR gate for outputting a given b i takes as input g i , and g N-1 ; and the gray-decoding circuitry outputs b N-1 =g N-1 .
characterised by adhesive patches · CPC title
involving processing of raw data to produce diagnostic data, e.g. for generating an image · CPC title
Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code · CPC title
for pulse systems (G01S7/52034 takes precedence) · CPC title
characterised by the arrangement of the transducer elements · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.