Multi-level pulser and related apparatus and methods

Patent metadata

Field	Value
Publication number	US-9933516-B2
Application number	US-201615288324-A
Country	US
Kind code	B2
Filing date	Oct 7, 2016
Priority date	Dec 2, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

Apparatus and methods are provided directed to a device, including at least one ultrasonic transducer, a multi-level pulser coupled to the at least one ultrasonic transducer; the multi-level pulser including a plurality of input terminals configured to receive respective input voltages, an output terminal configured to provide an output voltage, and a signal path between a first input terminal and the output terminal including a first transistor having a first conductivity type coupled to a first diode and, in parallel, a second transistor having a second conductivity type coupled to a second diode.

First claim

What is claimed is:

1. An apparatus for generating an ultrasound pulse, comprising:
a level shifter having an input terminal and an output terminal, the input terminal configured to receive an input signal having two or more states, the level shifter configured to output one or more control signals at the output terminal;
a pulser to communicate with the level shifter, the pulser configured to receive the one or more control signals from the level shifter and to provide a plurality of multi-level pulses corresponding to the one or more control pulses received from the level shifter; and
a capacitive micromachined ultrasonic transducer (CMUT) configured to receive the plurality of multi-level pulses from the pulser and convert each of the plurality of multi-level pulses to an acoustic ultrasound signal, each acoustic ultrasound signal corresponding to one of the plurality of multilevel pulses;
wherein the level shifter and the pulser are configured to dissipate heat when an ultrasound signal level is changed corresponding to the plurality of multi-level pulses.

2. The apparatus of claim 1 , wherein the level shifter and the pulser are integrated into a solid state chip.

3. The apparatus of claim 2 , wherein the level shifter, the pulser and the CMUT are integrated into the solid state chip.

4. The apparatus of claim 1 , wherein the level shifter further comprises an inverter connected to a capacitor, the inverter receiving at least two input voltages.

5. The apparatus of claim 1 , wherein the level shifter further comprises:
a voltage input terminal to receive an input voltage;
an output voltage terminal to provide an output voltage level-shifted from the input voltage;
one or more capacitors coupled between the voltage input terminal and the output voltage terminal; and
one or more diodes coupled in reverse-biased configuration between an input to an active high voltage element and a first voltage of a high voltage power supply.

6. The apparatus of claim 5 , wherein the active high voltage element comprises an inverter.

7. The apparatus of claim 1 , wherein the pulser further comprises:
a plurality of input terminals configured to receive respective input voltages;
an output terminal configured to provide an output voltage; and
a signal path between a first input terminal and the output terminal including a first transistor having a first conductivity type coupled to a first diode and, in parallel, a second transistor having a second conductivity type coupled to a second diode.

8. The apparatus of claim 7 , wherein the pulser comprises a controller to control a charge and discharge of an output capacitance to provide charge recycling.

9. The apparatus of claim 7 , comprising a plurality of signal paths between the first input terminal and the output terminal of the pulser, each signal path including a transistor having a first conductivity type coupled to a first diode and, in parallel, a transistor having a second conductivity type coupled to a second diode.

10. The apparatus of claim 9 , wherein the first conductivity type is pMOS and the second conductivity type is nMOS.

11. The apparatus of claim 7 , wherein the output voltage is equal to a predetermined input voltage.

12. The apparatus of claim 7 , wherein the first diode has an anode connected to the first transistor and a cathode connected to the output terminal of the pulser and wherein the second diode has a cathode connected to the second transistor and an anode connected to the output terminal of the pulser.

Assignees

• Butterfly Network Inc

Inventors

• Chen Kailiang
• Ralston Tyler S

Classifications

• H03K19/017545

  Coupling arrangements; Impedance matching circuits · CPC title

• G01S7/524 Primary

  Transmitters · CPC title

• G01S7/521

  Constructional features · CPC title

• A61B8/4483 Primary

  characterised by features of the ultrasound transducer · CPC title

• G01S7/5208

  with integration of processing functions inside probe or scanhead · CPC title