Methods of forming semiconductor devices, including forming a metal layer on source/drain regions

Patent metadata

Field	Value
Publication number	US-9601586-B1
Application number	US-201615017352-A
Country	US
Kind code	B1
Filing date	Feb 5, 2016
Priority date	Nov 2, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Methods of forming a semiconductor device are provided. A method of forming a semiconductor device includes forming a metal layer on source/drain regions of respective semiconductor structures, after replacing a dummy gate structure of the semiconductor device with a metal gate structure. The method includes forming a contact structure that overlaps the metal layer on one or more, but not all, of the semiconductor structures. Moreover, an insulating material is between the source/drain regions.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
replacing a dummy gate structure with a metal gate structure;
forming an opening over spaced-apart source/drain regions of respective semiconductor structures;
forming a metal layer in the opening, on the spaced-apart source/drain regions, after replacing the dummy gate structure with the metal gate structure, wherein the opening comprises a first opening that comprises a trench;
forming a first insulating material on the metal layer, wherein the first insulating material, and/or a second insulating material that is formed before forming the metal layer, is between the spaced-apart source/drain regions; and
forming, in the first insulating material, a contact structure that only partially overlaps the metal layer,
wherein forming the contact structure comprises:
forming, in the first insulating material, a second opening that is smaller than the trench; and
forming the contact structure in the second opening.

2. The method of claim 1 , wherein forming the opening comprises:
exposing at least a portion of each of the spaced-apart source/drain regions; or
exposing at least a portion of a silicide layer or etch stop layer on each of the spaced-apart source/drain regions.

3. The method of claim 2 , wherein:
adjacent ones of the source/drain regions are spaced apart from each other by at least five (5) nanometers;
the semiconductor structures comprise respective fin-shaped semiconductor structures; and
forming the contact structure comprises forming the contact structure over only one of the fin-shaped semiconductor structures.

4. The method of claim 3 , wherein:
forming the metal layer comprises forming the metal layer in the trench;
the method further comprises removing first portions of the metal layer from sidewalls of the trench; and
forming the first insulating material comprises forming the first insulating material on second portions of the metal layer that remain in the trench after removing the first portions of the metal layer from the sidewalls of the trench, wherein a first thickness of the first insulating material is equal to or thicker than a second thickness of the second portions of the metal layer, and wherein the second thickness of the second portions of the metal layer is between two (2) and twenty (20) nanometers.

5. The method of claim 1 ,
wherein forming the first insulating material comprises forming the first insulating material in the trench.

6. The method of claim 5 , wherein forming the metal layer comprises directionally depositing the metal layer in the trench so that the metal layer is thicker on the spaced-apart source/drain regions than on sidewalls of the trench.

7. The method of claim 1 , further comprising forming an etch stop layer on the spaced-apart source/drain regions,
wherein forming the opening comprises forming the opening while the etch stop layer is on the spaced-apart source/drain regions, before forming the metal layer.

8. The method of claim 7 , wherein forming the etch stop layer comprises forming the etch stop layer on top surfaces and side surfaces of the spaced-apart source/drain regions, before replacing the dummy gate structure with the metal gate structure.

9. The method of claim 8 , wherein forming the metal layer comprises forming the metal layer on the top surfaces and the side surfaces of the spaced-apart source/drain regions.

10. The method of claim 7 , wherein forming the etch stop layer comprises forming a silicide layer on the spaced-apart source/drain regions, before replacing the dummy gate structure with the metal gate structure.

11. The method of claim 10 , wherein forming the silicide layer comprises forming the silicide layer on top surfaces and side surfaces of the spaced-apart source/drain regions, before replacing the dummy gate structure with the metal gate structure.

12. The method of claim 1 , wherein forming the opening comprises forming the opening in the second insulating material, over at least a portion of each of the spaced-apart source/drain regions, before forming the metal layer.

13. The method of claim 12 ,
wherein forming the opening in the second insulating material comprises at least partially removing the second insulating material from between the spaced-apart source/drain regions of the respective semiconductor structures, and
wherein forming the metal layer comprises conformally forming the metal layer on top surfaces and side surfaces of the spaced-apart source/drain regions.

14. The method of claim 13 , wherein forming the first insulating material comprises forming the first insulating material between the side surfaces of the spaced-apart source/drain regions, after forming the metal layer on the top surfaces and the side surfaces of the spaced-apart source/drain regions.

15. The method of claim 1 , further comprising forming the second insulating material between side surfaces of the spaced-apart source/drain regions, before forming the metal layer,
wherein forming the metal layer comprises forming the metal layer on top surfaces of the spaced-apart source/drain regions and on the second insulating material that is between the side surfaces of the spaced-apart source/drain regions, and
wherein spaces between the spaced-apart source/drain regions comprise mostly the second insulating material.

16. A method of forming a semiconductor device, the method comprising:
forming unmerged source/drain regions on semiconductor structures;
replacing a dummy gate structure with a metal gate structure;
forming a metal layer that connects the unmerged source/drain regions with each other, after replacing the dummy gate structure with the metal gate structure; and
forming a contact structure that overlaps the metal layer on one or more, but not all, of the semiconductor structures,
wherein an insulating material is between the unmerged source/drain regions.

17. The method of claim 16 , wherein:
a thickness of the metal layer on the unmerged source/drain regions is between two (2) and twenty (20) nanometers;
adjacent ones of the unmerged source/drain regions are spaced apart from each other by at least five (5) nanometers; and
forming the contact structure comprises forming the contact structure on less than half of an entire uppermost surface of the metal layer.

18. The method of claim 16 , further comprising:
forming the dummy gate structure on a fin structure among the semiconductor structures, wherein replacing the dummy gate structure comprises:
removing the dummy gate structure; and
forming the metal gate structure in place of the dummy gate structure;

forming a trench that spans at least a portion of each of the unmerged source/drain regions, wherein forming the metal layer comprises forming the metal layer in the trench; and
forming the insulating material, and/or another insulating material, on the metal layer.

19. A method of forming a semiconductor device, the method comprising:
forming a metal layer on uppermost surfaces of unmerged source/drain regions of respective fin-shaped semiconductor structures, after a dummy gate structure of the semiconductor device has been replaced with a metal gate structure, wherein adjacent ones of the unmerged source/drain regions are spaced apart from each other by at least two (2) nanometers;
forming an insulating material on the metal layer, wherein the insulating material, and/or an isolation region that is formed before forming the metal layer, is between the unmerged

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kittl Jorge A
• Hong Joon Goo
• Rodder Mark S

Classifications

• H10D30/6219 Primary

  characterised by the source or drain electrodes · CPC title

• H10D84/0165

  the components including complementary IGFETs, e.g. CMOS devices · CPC title

• H10D30/0215 Primary

  using self-aligned selective metal deposition simultaneously on gate electrodes and the source regions or drain regions · CPC title

• H01L29/41791 Primary

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic