Conductive external connector structure and method of forming

Patent metadata

Field	Value
Publication number	US-11527504-B2
Application number	US-202016989461-A
Country	US
Kind code	B2
Filing date	Aug 10, 2020
Priority date	Nov 16, 2015
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a conductive contact over a semiconductor substrate;
a conductive pillar overlying the conductive contact, the conductive pillar comprising:
a first surface facing away from the semiconductor substrate; and
a second surface located at a right angle to the first surface, the second surface having a first portion and a second portion; and

a continuous flowable material fully covering the first surface and the first portion of the second surface, wherein the continuous flowable material exposes the second portion of the second surface, wherein the conductive pillar has a first width, wherein the first width is between about 38 μm to about 68 μm.

2. The semiconductor device of claim 1 , wherein the continuous flowable material has a height of between about 15 μm to about 40 μm.

3. The semiconductor device of claim 1 , wherein the conductive pillar has the first width a first distance away from the semiconductor substrate and a second width a second distance away from the semiconductor substrate, the second width being larger than the first width.

4. The semiconductor device of claim 3 , wherein the second width is between about 40 μm to about 70 μm.

5. The semiconductor device of claim 1 , wherein the continuous flowable material has a first thickness adjacent to the first portion of the second surface, wherein the first thickness is less than about 1 μm.

6. The semiconductor device of claim 1 , wherein the continuous flowable material has a composition of about 97.8% to about 98.6% of tin and about 1.4% to about 2.2% of silver.

7. The semiconductor device of claim 1 , wherein the continuous flowable material comprises tin and silver.

8. A semiconductor device comprising:
a continuous flowable cap separated from a dielectric layer by a first distance; and
a conductive pillar extending from the dielectric layer into the continuous flowable cap, the conductive pillar spanning the first distance, wherein the conductive pillar has a first height between bout 40 μm to about 70 μm.

9. The semiconductor device of claim 8 , wherein the first distance is 90% to 95% of the first height.

10. The semiconductor device of claim 8 , wherein the conductive pillar has a first width adjacent to the first distance and a second width over the first width, the first width being larger than the second width.

11. The semiconductor device of claim 10 , wherein the first width is between about 40 μm to about 70 μm.

12. The semiconductor device of claim 11 , wherein the second width is between about 38 μm to about 68 μm.

13. The semiconductor device of claim 10 , further comprising an intermetallic compound located adjacent to the continuous flowable material.

14. The semiconductor device of claim 8 , wherein the continuous flowable cap comprises tin and silver.

15. The semiconductor device of claim 14 , wherein the continuous flowable cap has a composition of about 97.8% to about 98.6% of tin and about 1.4% to about 2.2% of silver.

16. A semiconductor device comprising:
a first level comprising a passivation layer and a conductive pillar;
a second level comprising a continuous flowable material and the conductive pillar, wherein the continuous flowable material comprises a solder;
a third level comprising only the continuous flowable material, the third level being located over the second level; and
a fourth level comprising only the conductive pillar, the fourth level being between the second level and the first level, wherein the conductive pillar at the fourth level has a width of between about 38 μm and about 68 μm.

17. The semiconductor device of claim 16 , wherein the conductive pillar at the second level has a width of between about 40 μm and about 70 μm.

18. The semiconductor device of claim 16 , wherein the continuous flowable material at the second level has a thickness of less than about 1 μm.

19. The semiconductor device of claim 16 , wherein the continuous flowable material comprises tin and silver.

20. The semiconductor device of claim 19 , wherein the continuous flowable material has a composition of about 97.8% to about 98.6% of tin and about 1.4% to about 2.2% of silver.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shih Meng-Fu
• Lo Chun-Yen
• Huang Cheng-Lin
• Chen Wen-Ming
• Huang Chien-Ming
• Liu yuan-fu
• Cheng Yung-Chiuan
• Huang Wei-Chih
• Liu Chen-Hsun
• Chan Chien-Pin
• Hsu Yu-Nu
• Lin Chi-Hung
• Pang Te-Hsun
• Ku Chin-Yu

Classifications

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/019

  of bond pads · CPC title