Crystal seed layer for magnetic random access memory (MRAM)

Patent metadata

Field	Value
Publication number	US-11527275-B2
Application number	US-201916503692-A
Country	US
Kind code	B2
Filing date	Jul 5, 2019
Priority date	Sep 26, 2018
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a bottom electrode disposed over a semiconductor substrate;
a magnetic tunnel junction (MTJ) stack disposed over the bottom electrode; and
a conductive seed layer comprising a CrNiFe layer or CrNi layer separating the bottom electrode from the MTJ stack, the CrNiFe layer or CrNi layer comprising one or more crystals each having a maximum lateral width, where an average maximum lateral width of the one or more crystals is over 20 nanometers.

2. The semiconductor device of claim 1 , wherein the conductive seed layer comprises Cr x Ni 1-x-y Fe y , wherein x=0.1-0.5, y=0-0.2.

3. The semiconductor device of claim 1 , wherein a thickness of the conductive seed layer as defined between a top surface of the bottom electrode and a bottom surface of the MTJ stack is between 1 nm and 3 nm.

4. The semiconductor device of claim 1 , wherein the conductive seed layer comprises:
a CrNiFe layer disposed directly on the bottom electrode; and
a NiFe layer in direct contact with a top surface of the CrNiFe layer.

5. The semiconductor device of claim 1 , wherein the MTJ stack comprises:
a hard bias layer disposed over the conductive seed layer;
a reference layer disposed over the hard bias layer;
an anti-parallel coupling (APC) layer separating the hard bias layer from the reference layer;
a barrier layer over the reference layer;
a free layer over the barrier layer; and
a capping layer disposed over the free layer.

6. The semiconductor device of claim 5 , further comprising:
a top electrode disposed over the capping layer; and
a top electrode via disposed over the top electrode.

7. The semiconductor device of claim 1 , wherein the bottom electrode is formed over and is electrically coupled to a via, wherein sidewalls of the bottom electrode and the conductive seed layer are angled in a first direction that is opposite to a second direction in which sidewalls of the via are angled.

8. The semiconductor device of claim 1 , wherein the conductive seed layer includes only a single CrNiFe crystal between the bottom electrode and the MTJ stack.

9. The semiconductor device of claim 1 , wherein the one or more crystals each have a maximum height, and the average maximum lateral width of the one or more crystals is over three times an average maximum lateral height of the one or more crystals.

10. A method, comprising:
forming a bottom electrode layer;
forming a polycrystalline CrNiFe layer over the bottom electrode layer, wherein the polycrystalline CrNiFe layer includes CrNiFe crystals having an initial average grain size; and
forming a NiFe layer over and in direct contact with the polycrystalline CrNiFe layer wherein forming the NiFe layer induces recrystallization of the polycrystalline CrNiFe layer to establish a recrystallized polycrystalline CrNiFe layer, wherein the recrystallized polycrystalline CrNiFe layer includes enlarged CrNiFe crystals having an enlarged average grain size that is larger than the initial average grain size.

11. The method of claim 10 , further comprising:
forming a mask over the recrystallized polycrystalline CrNiFe layer; and
removing portions of the recrystallized polycrystalline CrNiFe layer and bottom electrode layer to establish a patterned recrystallized polycrystalline CrNiFe structure and bottom electrode structure, wherein the patterned recrystallized polycrystalline CrNiFe structure consists of a single CrNiFe crystal over the bottom electrode structure.

12. The method of claim 10 , further comprising:
removing the NiFe layer from over the recrystallized polycrystalline CrNiFe layer and thinning the recrystallized polycrystalline CrNiFe layer; and
after the NiFe layer has been removed, forming an MTJ stack in direct contact with an upper surface of the thinned recrystallized polycrystalline CrNiFe layer.

13. The method of claim 12 , wherein forming the MTJ stack comprises:
forming a hard bias layer over the polycrystalline CrNiFe layer;
forming an anti-parallel coupling (APC) layer over the hard bias layer;
forming a reference layer over the APC layer;
forming a barrier layer over the reference layer; and
forming a free layer over the barrier layer.

14. The method of claim 12 , further comprising:
forming a mask over the MTJ stack, and removing portions of the MTJ stack so a patterned MTJ stack remains in place over the recrystallized polycrystalline CrNiFe layer.

15. The method of claim 11 , further comprising:
forming an MTJ stack in direct contact with an upper surface of the NiFe layer.

16. The method of claim 10 , wherein the bottom electrode layer is formed over and is electrically coupled to a via, wherein sidewalls of the bottom electrode layer, seed layer structure, and re-crystallization-inducing layer are angled in a direction that is opposite to sidewalls of the via.

17. A semiconductor device, comprising:
a semiconductor substrate;
an interconnect structure disposed over the semiconductor substrate;
a bottom electrode disposed over the semiconductor substrate within the interconnect structure;
a conductive seed layer comprising a CrNiFe layer or a CrNi layer disposed on the bottom electrode;
a magnetic tunnel junction (MTJ) disposed over the conductive seed layer and separated from the bottom electrode by the conductive seed layer; and
a top electrode disposed over the MTJ;
wherein the conductive seed layer includes only a single CrNiFe crystal separating the bottom electrode and the MTJ.

18. The semiconductor device of claim 17 , wherein the bottom electrode is formed over and electrically coupled to a via in the interconnect structure, wherein sidewalls of the bottom electrode, seed layer structure, and re-crystallization-inducing layer are angled in a direction that is opposite to sidewalls of the via.

19. The semiconductor device of claim 17 , wherein the conductive seed layer comprises Cr x Ni 1-x-y Fe y , wherein x=0.1-0.5, y=0-0.2.

20. The semiconductor device of claim 17 , wherein a thickness of the conductive seed layer as defined between a top surface of the bottom electrode and a bottom surface of the MTJ is between 1 nm and 3 nm.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Tsann
• Ying Ji-Feng
• Lai Chih-Chung

Classifications

• H01F10/3272

  by use of anti-parallel coupled [APC] ferromagnetic layers, e.g. artificial ferrimagnets [AFI], artificial [AAF] or synthetic [SAF] anti-ferromagnets · CPC title

• H01F41/302

  for applying spin-exchange-coupled multilayers, e.g. nanostructured superlattices (spin-exchange-coupled multilayers H01F10/32) · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01F41/34

  in patterns, e.g. by lithography · CPC title

• H01F10/3259

  Spin-exchange-coupled multilayers comprising at least a nanooxide layer [NOL], e.g. with a NOL spacer · CPC title