Techniques for mram mtj top electrode connection

Patent metadata

Field	Value
Publication number	US-2016380183-A1
Application number	US-201615000289-A
Country	US
Kind code	A1
Filing date	Jan 19, 2016
Priority date	Jun 25, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in direct electrical contact with a lower surface of the upper metal layer.

First claim

What is claimed is:

1 . An integrated circuit, comprising:
a semiconductor substrate; an interconnect structure disposed over the semiconductor substrate, and including a plurality of dielectric layers and a plurality of metal layers stacked over one another in alternating fashion, wherein the plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer; a bottom electrode disposed over and in electrical contact with the lower metal layer; a magnetic tunneling junction (MTJ) disposed over an upper surface of bottom electrode; and a top electrode disposed over an upper surface of the MTJ and being in direct electrical contact with a lower surface of the upper metal layer.

2 . The integrated circuit of claim 1 , further comprising:
MRAM sidewall spacers disposed along outer sidewalls of the top electrode and MTJ, wherein the MRAM sidewall spacers have upper portions that extend upwardly beyond an upper surface of the top electrode and into a recess in a lower surface of the upper metal layer.

3 . The integrated circuit of claim 2 , wherein uppermost surfaces of the MRAM sidewall spacers are rounded or tapered.

4 . The integrated circuit of claim 1 , further comprising:
MRAM sidewall spacers having inner upper sidewalls that are separated by a first distance near the top electrode, and having inner lower sidewalls that are spaced apart by a second distance, wherein the second distance is greater than the first distance.

5 . The integrated circuit of claim 4 , wherein outer lower sidewalls of the MRAM sidewall spacers are vertical or substantially vertical, and meet outer upper sidewalls of the MRAM sidewall spacers at a ledge or shoulder region.

6 . The integrated circuit of claim 4 , further comprising:
a dielectric liner that conformally overlies outer sidewalls of the MRAM sidewall spacers.

7 . A magnetoresistive random-access memory (MRAM) cell disposed on a semiconductor substrate, the MRAM cell including:
a bottom electrode disposed over the semiconductor substrate; a magnetic tunneling junction (MTJ) disposed over the bottom electrode; a top electrode disposed over an upper surface of the MTJ; and a metal line disposed over the top electrode and in direct physical and electrical contact with the top electrode without a via or contact extending between the metal line and top electrode.

8 . The MRAM cell of claim 7 , further comprising:
MRAM sidewall spacers disposed along outer sidewalls of the top electrode and MTJ, wherein the MRAM sidewall spacers have upper portions that extend upwardly beyond an upper surface of the top electrode and into a lower surface region of the metal line.

9 . The MRAM cell of claim 8 , wherein the MRAM spacers have lowermost surfaces that rest on an upper surface of the bottom electrode.

10 . The MRAM cell of claim 8 , wherein the MRAM sidewall spacers have innermost upper sidewalls that are separated by a first distance near the top electrode, and having inner lowermost sidewalls that are spaced apart by a second distance, wherein the second distance is greater than the first distance.

11 . The MRAM cell of claim 10 , wherein the lowermost sidewalls are angled at an angle of other than 90-degrees as measured relative to a normal line passing through an upper surface of the bottom electrode.

12 . The MRAM cell of claim 11 , wherein an uppermost surface of each MRAM sidewall spacer is rounded or tapered extending downward from both sides of a peak in the MRAM sidewall spacer, and wherein a dielectric liner that conformally overlies outer sidewalls of the MRAM sidewall spacers.

13 . A method for manufacturing a magnetoresistive random access memory (MRAM) cell, the method including:
forming an etch stop layer disposed over an upper surface of a dielectric layer, wherein the etch stop layer exhibits an opening that leaves at least a portion of an upper surface of an underlying metal line exposed; forming a bottom electrode layer over the etch stop layer, the bottom electrode layer extends downward through the opening to physically and electrically connect to the underlying metal line; forming a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; forming a top electrode over the magnetic tunnel junction layer; and forming an upper metal layer in direct electrical and physical contact with an upper portion of the top electrode.

14 . The method of claim 13 , wherein forming the top electrode further comprises:
forming a top electrode layer over the MTJ layer; forming a hardmask over the top electrode layer; and patterning the MTJ layer and top electrode layer to remove portions of both the MTJ layer and top electrode layer not covered by the hardmask to form the top electrode and MTJ; forming a conformal MRAM sidewall spacer layer disposed along outer sidewalls of the top electrode and the MTJ and extending over an upper surface of the hardmask.

15 . The method of claim 14 , wherein the hardmask includes an SiO 2 layer and an SiON layer over the SiO 2 layer.

16 . The method of claim 15 , further comprising:
performing a first etch on the MRAM sidewall spacer layer to remove lateral portions of the MRAM sidewall spacer layer and leaving the SiO 2 layer over the top electrode and leaving portions of the MRAM sidewall spacer layer extending upwardly along sidewalls of the SiO 2 layer.

17 . The method of claim 15 , wherein the hardmask includes a silicon nitride layer between the SiO 2 layer and the top electrode.

18 . The method of claim 16 , wherein a lowermost portion of the SiO 2 layer directly abuts an upper surface of the top electrode.

19 . The method of claim 16 , further comprising:
performing a second etch to selectively remove the SiO 2 layer, leaving the portions of the MRAM sidewall spacer layer extending upwardly past an upper surface of the top electrode.

20 . The method of claim 19 , further comprising:
forming a dielectric layer over the portions of the MRAM sidewall spacer layer and top electrode; and forming trench and via openings in the dielectric layer, wherein a trench opening exposes upper surfaces of the top electrode and portions of the MRAM sidewall spacer layer; and filling the trench and via openings with a conductive material that directly abuts an upper surface of the top electrode.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Harry-Hak-Lay
• Hsu Chem-Yow
• Liu Shih-Chang

Classifications

• H10W20/01

  Manufacture or treatment · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N59/00 Primary

  Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00 (MRAM devices H10B61/00) · CPC title

• H10N50/80

  Constructional details · CPC title