Epitaxial layers on contact electrodes for thin- film transistors

Patent metadata

Field	Value
Publication number	US-11522060-B2
Application number	US-201816142036-A
Country	US
Kind code	B2
Filing date	Sep 26, 2018
Priority date	Sep 26, 2018
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a transistor above the substrate, wherein the transistor includes:
a contact electrode above the substrate, wherein the contact electrode includes a conductive material;
an epitaxial layer above the contact electrode;
a channel layer above the epitaxial layer and above the contact electrode, wherein the channel layer is in direct physical contact with the epitaxial layer, the channel layer includes a channel material, a conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material, and a bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material; and
a gate electrode above the channel layer, and separated from the channel layer by a gate dielectric layer.

2. The semiconductor device of claim 1 , wherein the contact electrode is a source electrode or a drain electrode.

3. The semiconductor device of claim 1 , wherein the epitaxial layer includes a material selected from a group consisting of Ga 2 O 3 , ZnO, In 2 O 3 , Si, Ge, AlN, GaN, InN, AIP, GaP, InP, AlAs, GaAs, InAs, AlSb, GaSb, SnO, ITO, and InSb.

4. The semiconductor device of claim 1 , wherein the epitaxial layer and the contact electrode are completely under the channel layer.

5. The semiconductor device of claim 1 , wherein the epitaxial layer has a width of about 5 nm to 100 nm, and the channel layer has a width of about 100 nm to 1000 nm.

6. The semiconductor device of claim 1 , wherein the epitaxial layer include multiple epitaxial sublayers.

7. The semiconductor device of claim 6 , wherein the epitaxial layer includes a first epitaxial sublayer including GaAs, a second epitaxial sublayer including InGaAs, and a third epitaxial sublayer including InAs.

8. The semiconductor device of claim 1 , further comprising:
the gate dielectric layer between the channel layer and the gate electrode, wherein the gate dielectric layer includes a material selected from a group consisting of silicon and oxygen; silicon and nitrogen; yttrium and oxygen; silicon, oxygen, and nitrogen; aluminum and oxygen; hafnium and oxygen; tantalum and oxygen; and titanium and oxygen.

9. The semiconductor device of claim 1 , wherein the channel layer includes a material selected from a group consisting of indium doped zinc oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature polycrystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, zinc oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, silicene, Si 2 BN, stanene, phosphorene, molybdenite, poly-III-V like InAs, InGaAs, InP, amorphous InGaZnO (a-IGZO), crystal-like InGaZnO (c-IGZO), GaZnON, ZnON, or C-Axis Aligned Crystal (CAAC), molybdenum and sulfur, and a group-VI transition metal dichalcogenide.

10. The semiconductor device of claim 1 , wherein the gate electrode or the contact electrode includes a material selected from a group consisting of titanium (Ti), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), Mn, Co, Ir, Rh, Te, Sr, Te, Ru, Ag, Re, and an alloy of Ti, Mo, Au, Pt, Al, Ni, Cu, Cr, TiN, TiAlN, HfAlN, or InAlO.

11. The semiconductor device of claim 1 , wherein the substrate includes a silicon substrate, a glass substrate, a metal substrate, or a plastic substrate.

12. The semiconductor device of claim 1 , wherein the transistor is above an interconnect that is above the substrate.

13. A semiconductor device, comprising:
a substrate;
a transistor above the substrate, wherein the transistor includes:
a contact electrode above the substrate, wherein the contact electrode includes a conductive material;
an epitaxial layer above and in direct physical contact with the contact electrode;
a channel layer above the epitaxial layer and above the contact electrode, wherein the channel layer includes a channel material, a conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material, and a bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material; and
a gate electrode above the channel layer, and separated from the channel layer by a gate dielectric layer.

14. The semiconductor device of claim 13 , wherein the contact electrode is a source electrode or a drain electrode.

15. The semiconductor device of claim 13 , wherein the epitaxial layer includes a material selected from a group consisting of Ga 2 O 3 , ZnO, In 2 O 3 , Si, Ge, AlN, GaN, InN, AIP, GaP, InP, AlAs, GaAs, InAs, AlSb, GaSb, SnO, ITO, and InSb.

16. The semiconductor device of claim 13 , wherein the epitaxial layer and the contact electrode are completely under the channel layer.

17. The semiconductor device of claim 13 , wherein the epitaxial layer has a width of about 5 nm to 100 nm, and the channel layer has a width of about 100 nm to 1000 nm.

18. The semiconductor device of claim 13 , wherein the epitaxial layer include multiple epitaxial sublayers.

19. The semiconductor device of claim 18 , wherein the epitaxial layer includes a first epitaxial sublayer including GaAs, a second epitaxial sublayer including InGaAs, and a third epitaxial sublayer including InAs.

20. The semiconductor device of claim 13 , further comprising:
the gate dielectric layer between the channel layer and the gate electrode, wherein the gate dielectric layer includes a material selected from a group consisting of silicon and oxygen; silicon and nitrogen; yttrium and oxygen; silicon, oxygen, and nitrogen; aluminum and oxygen; hafnium and oxygen; tantalum and oxygen; and titanium and oxygen.

21. The semiconductor device of claim 13 , wherein the channel layer includes a material selected from a group consisting of indium doped zinc oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature polycrystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, zinc oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, silicene, Si 2 BN, stanene, phosphorene, molybdenite, poly-III-V like InAs, InGaAs, InP, amorphous InGaZnO (a-IGZO), crystal-like InGaZnO (c-IGZO), GaZnON, ZnON, or C-Axis Aligned Crystal (CAAC), molybdenum and sulfur, and a group-VI transition metal dichalcogenide.

22. The semiconductor device of claim 13 , wherein the gate electrode or the contact electrode includes a material selected from a group consisting of titanium (Ti), molybdenum (Mo), gold (Au), platinum (

Assignees

• Intel Corp

Inventors

• Sung Seung Hoon
• Weber Justin
• Metz Matthew
• Sen Gupta Arnab
• Sharma Abhishek
• Chu-Kung Benjamin
• Dewey Gilbert
• Kuo Charles
• Haratipour Nazila
• Shivaraman Shriram
• Le Van H
• Ghani Tahir
• Kavalieros Jack T
• Ma Sean

Classifications

• H10P14/3442 Primary

  N-type · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/3436

  being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title

• H10P14/3221

  Arsenides · CPC title